• Proceedings of the KIPE Conference
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• 2018.07a
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• pp.210-212
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• 2018

A new switching mode has been proposed to obtain high power factor and low THD in single stage AC-DC converter. The conventional voltage mode control in critical conduction mode distorts input current shape with poor THD in flyback topology. Once TRIAC dimmer is connected, visible flicker in the LED lamp is easily detected due to a lack of TRAIC holding current near the input voltage zero cross. The newly proposed method can shape the input current by providing a desired reference voltage so that low THD is obtained by ideal sinusoidal input current in case of no dimmer connection and flat input current performs good TRIAC dimmer compatibility in phase-cut dimming condition. To confirm the validity of the proposed method, theoretical analysis and experimental result from 8W dimmable LED lighting system are presented.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.11
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• pp.1571-1577
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• 2015

A new mixed mode control of constant power and constant current for resistance spot welding inverter is proposed to improve the weld quality. The conventional control scheme adopts constant current or constant power control mode, however, it is not easy to guarantee the high weld quality because of the nonlinear resistance characteristics of the welding point. The proposed method utilizes the nonlinear characteristics by measuring the dynamic resistance in real time. Therefore, it is possible for the welder to be controlled adaptively depending on the welding state. Experimental results show that the proposed control scheme improves the weld quality by 6.8 times compared with the conventional constant current mode control.

• Journal of Power Electronics
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• v.5 no.2
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• pp.104-108
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• 2005

This paper presents the performance improvement of voltage-mode controlled interleaved synchronous buck converters. This is a voltage-mode controlled scheme, where the controllers do not need an external saw-tooth generator for PWM generation and the loop design is easier. The controller implementation requires only a single error amplifier and gives almost current mode control performance. The control scheme uses voltage feedback with two loops similar to current mode control: one for the slow outer loop and the other for the faster inner PWM control loop. To improve the performance of the converter system a coupled inductor is used. This coupled inductor reduces the magnetic size and also improves the converter's transient performance without increasing the steady-state current ripple. The effectiveness of the proposed control scheme is demonstrated through PSIM simulations.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.2
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• pp.104-109
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• 2009

At a lower supply voltage, voltage-mode drivers draw less current than current-mode drivers. In this paper, we newly propose a voltage-mode driver with an additional current path that reduces the output voltage swing without the need for complicated additional circuitry, compared to conventional voltage-mode drivers. The prototype driver is fabriccated in a 0.13-$^{\mu}m$ CMOS technology and used to transmit data streams at the rate of 2.5 Gb/s. Deemphasis is also implemented for the compensation of channel attenuation. With a 1.2-V supply, it dissipates 8.0 mA for a 400-mV output voltage swing.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2003.02a
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• pp.43-46
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• 2003

The dc reactor type high-Tc superconducting fault current limiter(SFCL) is composed of three parts, a power converter, a magnetic core reactor(MCR) and a dc reactor. This study concerned with the power converter of the DC reactor type high-Tc SFCL. The rectifying devices which power converter of 6.6kV/200A SFCL consists of have to endure high voltage. We propose the dual mode power converter to reduce the voltage which each rectifying device endures. In the single phase the experiment and simulation of dual mode power converter and the simulation of power converter with one bridge rectifier are performed. The current of each system with different power converter has a same tendency and the voltage which rectifying device of dual mode power converter endures is reduced in half by comparison with that of power converter with one bridge rectifier. We found dual mode power converter can be applied to SFCL.

• Journal of Power Electronics
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• v.11 no.4
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• pp.520-526
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• 2011

This paper presents a balanced soft-chopping circuit and a modified PI controller for a high speed 4/2 Switched Reluctance Motor (SRM) with a 16 pulse per revolution encoder. The proposed balanced soft-chopping circuit can supply double the switching frequency in the fixed switching frequency of power devices to reduce current ripple. The modified PI controller uses maximum voltage, back-emf voltage and PI control modes to overcome the over-shoot current due to the time delay effect of current sensing. The maximum voltage mode can supply a fast excitation current with consideration of the hardware time delay. Then the back-emf voltage mode can suppress the current over-shoot with consideration of the feedback signal delay. Finally, the PI control mode can adjust the phase current to a desired value with a fast switching frequency due to the proposed balanced soft-chopping technology.

• Journal of Power Electronics
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• v.12 no.5
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• pp.715-722
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• 2012

New discrete time domain models for the peak current controlled (PCC) power LED drivers in continuous conduction mode include for the first time the effects of the time delay in the pulse-width-modulator. Realistic amounts of time delay are found to have significant effects on the average output LED current and on the critical inductor value at the boundary between the two conduction modes. Especially, the time delay can provide an accurate LED current for the PCC buck converter with a wide input voltage. The models can also predict the critical inductor value at the mode boundary as functions of the input voltage and the time delay. The overshoot of the peak inductor current due to the time delay results in the increase of the average output current and the reduction of the critical inductor value at the mode boundary in all converters. Experimental results are presented for the PCC buck LED driver with constant-frequency controller.

• Journal of Power Electronics
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• v.19 no.6
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• pp.1477-1485
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• 2019

This paper proposes an effective model predictive current control (MPCC) that involves using 10 virtual voltage vectors to reduce the current harmonics and common-mode voltage (CMV) for a two-level five-phase voltage source inverter (VSI). In the proposed scheme, 10 virtual voltage vectors are included to reduce the CMV and low-order current harmonics. These virtual voltage vectors are employed as the input control set for the MPCC. Among the 10 virtual voltage vectors, two are applied throughout the whole sampling period to reduce current ripples. The two selected virtual voltage vectors are based on location information of the reference voltage vector, and their duration times are calculated using a simple algorithm. This significantly reduces the computational burden. Simulation and experimental results are provided to verify the effectiveness of the proposed scheme.

• The Transactions of the Korean Institute of Power Electronics
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• v.5 no.5
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• pp.443-450
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• 2000

A PWM inverter for an induction motor often has a problem with a high frequency leakage current that flows through stray capacitors between stator windings and a motor frame to ground. This paper proposes a new type of Active Common Mode Voltage Canceler circuit for the reduction of common mode voltage and high frequency leakage current generated by the PWM VSI-fed induction motor drives. The compensating voltage applied by the common made voltage canceler has the same amplitude as, hut the opposite polarity to, the common mode voltage by PWM Inverter. Therefore, common mode voltage and high frequency leakage current can be canceled. The proposed circuit consists of four-level half-bridge inverter and common-mode transformer. Simulated and experimental results show that common mode voltage canceler makes significant contributions to reducing a high frequency leakage current.

• The Journal of the Korea institute of electronic communication sciences
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• v.3 no.2
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• pp.79-85
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• 2008

It is important to consider the life of battery and low power operation for various wireless communications. Thus, Analog current-mode signal processing with SI circuit has been taken notice of in designing the LSI for wireless communications. However, in current mode signal processsing, current memory circuit has a problem called clock-feedthrough. In this paper, we examine the connection of CMOS switch that is the common solution of clock-feedthrough and calculate the relation of width between CMOS switch for design methodology for improvement of current memory. As a result of simulation, when the width of memory MOS is 20um, ratio of input current and bias current is 0.3, the width relation in CMOS switch is obtained with $W_{Mp}=5.62W_{Mn}+1.6$, for the nMOS width of 2~6um in CMOS switch. And from the same simulation condition, it is obtained with $W_{Mp}=2.05W_{Mn}+23$ for the nMOS width of 6~10um in CMOS switch. Then the defined width relation of MOS transistor will be useful guidance in design for improvement of current memory.