• The Transactions of the Korean Institute of Power Electronics
• /
• v.7 no.1
• /
• pp.81-90
• /
• 2002

This paper presents an Implementation of digital high-performance position sensorless control system of Reluctance Synchronous Motor(RSM) drives with Direct Torque Control(DTC). The system consists of stator flux observer, speed and torque estimator, two digital hysteresis controllers, an optimal switching look-up table, Insulated Gate Bipolar Transistor(IGBT) voltage source inverter, and TMS320C31 DSP board. The stator flux observer Is based on the combined voltage and current model with stator flux feedback adaptive control of which inputs are current and voltage sensed on motor terminal for wide speed range. In order to prove the suggested sensorless control algorithm for industrial field application, we have some simulation and actual experiment at low and high speed range. The developed high-performance speed control by fully digital system are shown a good response characteristic of control results and high performance features using 1.0[kW] RSM having 2.57 reluctance ratio of $L_d/L_q$.

• Journal of Power Electronics
• /
• v.16 no.2
• /
• pp.464-472
• /
• 2016

This study applies the selective harmonic elimination (SHE) technique to design and operate a regulated AC/DC/AC power supply suitable for maritime military applications and underground trains. The input is a single 50/60 Hz AC voltage, and the output is a 400 Hz regulated voltage. The switching angles for a multi-level inverter and transformer turns ratio are determined to operate with special connected transformers with equal power ratings and produce an almost sinusoidal current. As a result of its capability of directly controlling harmonics, the SHE technique is applicable to apparatus with congenital immunity to specific harmonics, such as series-connected transformers, which are specially designed to equally share the total load power. In the present work, a single-phase 50/60 Hz input source is rectified via a semi-controlled bridge rectifier to control DC voltage levels and thereby regulate the output load voltage at a constant level. The DC-rectified voltage then supplies six single-phase quazi-square H-bridge inverters, each of which supplies the primary of a single-phase transformer. The secondaries of the six transformers are connected in series. Through off-line calculation, the switching angles of the six inverters and the turns ratios of the six transformers are designed to ensure equal power distribution for the transformers. The SHE technique is also employed to eliminate the higher-order harmonics of the output voltage. A digital implementation is carried out to determine the switching angles. Theoretical results are demonstrated, and a scaled-down experimental 600 VA prototype is built to verify the validity of the proposed system.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2011.02a
• /
• pp.479-479
• /
• 2011

Flexible inverters based on complementary thin-film transistor (CTFTs) are important because they have low power consumption and other advantages over single type TFT inverters. In addition, integrated CTFTs in flexible electronic circuits on low-cost, large area and mechanically flexible substrates have potentials in various applications such as radio-frequency identification tags (RFIDs), sensors, and backplanes for flexible displays. In this work, we introduce flexible complementary inverters using pentacene and amorphous indium gallium zinc oxide (IGZO) for the p-channel and n-channel, respectively. The CTFTs were fabricated on polyimide (PI) substrate. Firstly, a thin poly-4-vinyl phenol (PVP) layer was spin coated on PI substrate to make a smooth surface with rms surface roughness of 0.3 nm, which was required to grow high quality IGZO layers. Then, Ni gate electrode was deposited on the PVP layer by e-beam evaporator. 400-nm-thick PVP and 20-nm-thick ALD Al2O3 dielectric was deposited in sequence as a double gate dielectric layer for high flexibility and low leakage current. Then, IGZO and pentacene semiconductor layers were deposited by rf sputter and thermal evaporator, respectively, using shadow masks. Finally, Al and Au source/drain electrodes of 70 nm were respectively deposited on each semiconductor layer using shadow masks by thermal evaporator. Basic electrical characteristics of individual transistors and the whole CTFTs were measured by a semiconductor parameter analyzer (HP4145B, Agilent Technologies) at room temperature in the dark. Performance of those devices then was measured under static and dynamic mechanical deformation. Effects of cyclic bending were also examined. The voltage transfer characteristics (Vout- Vin) and voltage gain (-dVout/dVin) of flexible inverter circuit were analyzed and the effects of mechanical bending will be discussed in detail.

• The Transactions of the Korean Institute of Electrical Engineers B
• /
• v.54 no.2
• /
• pp.94-100
• /
• 2005

Korea Electrotechnology Research Institute(KERI) has successfully developed a 100hp-1800rpm-class high temperature superconducting(HTS) motor with high efficiency under partnership with Doosan Heavy Industries & Construction Co. Ltd. This motor has a HTS field winding and an air-cooled stator. The advantages of HTS motor can be represented by a reduction of 50% in both losses and size compared to conventional motors of the same rating. The cooling system is based on the heat transfer mechanism of the thermosyphon by using GM cryocooler as cooling source. The cold head is in contact with the condenser of a Ne-filled thermosyphon. Independently, the rotor assembly was tested at the stationary state and combined with stator. The HTS field winding could be cooled into below 30K. Test of open-circuit characteristics(OCC) and short-circuit characteristics(SCC) and load test with resistive load bank were conducted in generator mode. Also, load tests in motor mode driven by inverter were finished at KERI. Maximum operating current of field winding at 30K was 120A. From OCC and SCC test results synchronous inductance and synchronous reactance were 2.4mH, 0.49pu, respectively. Efficiency of this HTS machine was 93.3% in full load(100hp) test. This paper will present design, construction. and experimental test results of the 100hp HTS machine.

• Electrical & Electronic Materials
• /
• v.9 no.1
• /
• pp.30-37
• /
• 1996

Previously, crystallization of a-Si:H films on glass substrates were limited to anneal temperature below 600.deg. C, over 10 hours to avoid glass shrinkage. Our study indicates that the crystallization is strongly influenced by anneal temperature and weakly affected by anneal duration time. Because of the high temperature process and nonconducting substrate requirements for poly-Si TFTs, the employed substrates were limited to quartz, sapphire, and oxidized Si wafer. We report on poly-Si TFT's using high temperature anneal on a Si:H/Mo structures. The metal Mo substrate was stable enough to allow 1000.deg. C anneal. A novel TFT fabrication was achieved by using part of the Mo substrate as drain and source ohmic contact electrode. The as-grown a-Si:H TFT was compared to anneal treated poly-Si TFT'S. Defect induced trap states of TFT's were examined using the thermally stimulated current (TSC) method. In some case, the poly-Si grain boundaries were passivated by hydrogen. A-SI:H and poly-Si TFT characteristics were investigated using an inverted staggered type TFT. The poly -Si films were achieved by various anneal techniques; isothermal, RTA, and excimer laser anneal. The TFT on as grown a-Si:H exhibited a low field effect mobility, transconductance, and high gate threshold voltage. Some films were annealed at temperatures from 200 to >$1000^{\circ}C$ The TFT on poly-Si showed an improved $I_on$$I_off$ ratio of $10_6$, reduced gate threshold voltage, and increased field effect mobility by three orders. Inverter operation was examined to verify logic circuit application using the poly Si TFTs.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.19 no.1
• /
• pp.65-76
• /
• 2024

With the recent activation of the offshore wind power industry, there has been a development of power plants with a scale exceeding 400MW, comparable to traditional thermal power plants. Renewable energy, characterized by intermittency depending on the energy source, is a prominent feature of modern renewable power generation facilities, which are structured based on controllable inverter technology. As the integration of renewable energy sources into the grid expands, the grid codes for power system connection are progressively becoming more defined, leading to active discussions and evaluations in this area. In this paper, we propose a method for selecting optimal reactive power compensation capacity when multiple offshore wind farms are integrated and connected through a shared interconnection facility to comply with grid codes. Based on the requirements of the grid code, we analyze the reactive power compensation and excessive stability of the 400MW wind power generation site under development in the southwest sea of Jeonbuk. This analysis involves constructing a generation site database using PSS/E (Power System Simulation for Engineering), incorporating turbine layouts and cable data. The study calculates reactive power due to charging current in internal and external network cables and determines the reactive power compensation capacity at the interconnection point. Additionally, static and dynamic stability assessments are conducted by integrating with the power system database.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.1
• /
• pp.91-105
• /
• 2016

Carbon Nanotube Field-Effect Transistors (CNTFETs) have been studied as candidates for post Si CMOS owing to the better electrostatic control and high mobility. To enhance the immunity against short - channel effects (SCEs), the novel channel and gate engineered architectures have been proposed to improve CNTFETs performance. This work presents a comprehensive study of the influence of channel and gate engineering on the CNTFET switching, high frequency and circuit level performance of carbon nanotube field-effect transistors (CNTFETs). At device level, the effects of channel and gate engineering on the switching and high frequency characteristics for CNTFET have been theoretically investigated by using a quantum kinetic model. This model is based on two-dimensional non-equilibrium Green's functions (NEGF) solved self - consistently with Poisson's equations. It is revealed that hetero - material - gate and lightly doped drain and source CNTFET (HMG - LDDS - CNTFET) structure can significantly reduce leakage current, enhance control ability of the gate on channel, improve the switching speed, and is more suitable for use in low power, high frequency circuits. At circuit level, using the HSPICE with look - up table(LUT) based Verilog - A models, the impact of the channel and gate engineering on basic digital circuits (inverter, static random access memory cell) have been investigated systematically. The performance parameters of circuits have been calculated and the optimum metal gate workfunction combinations of ${\Phi}_{M1}/{\Phi}_{M2}$ have been concluded in terms of power consumption, average delay, stability, energy consumption and power - delay product (PDP). In addition, we discuss and compare the CNTFET-based circuit designs of various logic gates, including ternary and binary logic. Simulation results indicate that LDDS - HMG - CNTFET circuits with ternary logic gate design have significantly better performance in comparison with other structures.