• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.215-217
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• 2006

This paper presents an area efficient 8-bit current digital to analog convector (DAC) which is applied to 240 channels Active Matrix - Organic Light Emitting Diode (AMOLED) data driver. The proposed circuit constitutes 4-bit binary weighted current DAC and 4-bit switched capacitor cyclic DAC. The proposed DAC has about 70% smaller area than that of the typical binary weighted current DAC. We overcome sampling time by reducing the number of repetition phases so that it can display 8-bit gray scale image.

• Proceedings of the KIEE Conference
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• 1995.11a
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• pp.281-283
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• 1995

Deadbeat controlled PWM Inverter is realized. This PWM inverter performs the instantaneous control method which is based on the real-time digital feedback control and the microprocessor-based deadbeat control. For the deadbeat current controller, the system's order becomes a high order and increases computation delay time. Therefore, The delay tine produces current ripple. To minimize the current ripple, a new method based on deadbeat control theory for current regulation is proposed. It is constructed by a reduced-order state observer which predicts the output current in next sampling instant.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.34 no.9
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• pp.361-367
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• 1985

A new injection method is proposed for active power filters to eliminate AC harmonics in ac input current of nonlinear loads such as rectifiers. By injecting the PWM current determined by the proposed injection method, all the harmonics up to order nn can be eliminated to exactly zero. This PWM injection current can be generated by sampling total harmonic wave at the rate of M and the sampled values are converted into the proposed PWM wave with N pulse-width variables and adjustable current magnitude Im. These variables are deetermined by solving a set of N nonlinear harmonic equations and the harmonic-elimination characteristics of the new injection are investigated through digital computer sinmulation. Also by comparing between the simulated results and the ones synthesized by data stored in EPROM, the possibility of the suggested injection method can be shown.

• Journal of Electrical Engineering and information Science
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• v.2 no.4
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• pp.86-91
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• 1997

A method of detecting the three phase currents for a voltage-fed pusle width modulated(PWM) inverter is proposed, where only one current sensor is utilized on the dc-link. The proposed method has the constant sampling time by employing he modified space-vector PWM technique which generates the rearranged switching pattern to detect a phase current from ad dc-link current. Experimental results show that eh proposed scheme provides a very good detection method of three phase currents without phase current sensors. This method is very simple and has small detection errors.

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.797-800
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• 1987

A new current control scheme is suggest.ed which is suitable for ac servo inverter drives. The scheme uses a simple block diagram to produce the reference stator voltage vector, and the vector nearest to it is chosen for switching. With the same arrangment three kinds of operation modes are possible : (1) constant rate sampling, (2) constant current deviation, (3) adaptive current deviation. In mode (1) current deviation after one period is minimized, while in mode (2) and (3) intervals between switchings are maximized.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.49 no.4
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• pp.272-281
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• 2000

This paper deals with the parallel operation of several numbers of PWM converters for a high speed railway train application. Several considerations are made to reduce the transformer interaction which can cause a current control problem in severe case. Also, in this paper, novel control strategy is proposed to achieve a harmonic free primary-side current control under a light load condition using one current sensor independent of the number of converters. In addition, the modified predictive current controller, which is suitable to a digital current controller with a relatively large sampling period, is used. Finally, to verify the system validity, digital control system with TMS320C44 micro-processor and small scale simulator are made and tested.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.12
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• pp.1721-1724
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• 2017

This paper presents a numerical optimization technique to reduce input current and torque ripple of the low voltage BLDC motor using core, coil and switching angle optimization. The optimization technique is employed using the generalized response surface method(RSM) and sampling minimization technique with FEM. A 50W 24V BLDC motor is used to verify the proposed algorithm. As optimizing results, the input current is reduced from 2.46 to 2.11[A], and the input power is reduced from 59 [W] to 51 [W] at the speed of 1000 [rpm]. Also, applied the same optimization algorithm, the torque ripple is reduced about 7.4 %. It is confirmed that the proposed technique is a reasonably useful tool to reduce the consuming current and torque ripple of the low voltage BLDC motor for a compact and efficient design.

• The Transactions of the Korean Institute of Power Electronics
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• v.17 no.5
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• pp.388-392
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• 2012

In this paper, a sampler model for the P-type current mode control employing low pass filter is proposed. Even though the frequency response of the compensator used in a P-type current mode control employing low pass filter is similar to that of P-type compensator, the sampler model has to be obtained from the method used in PI-type current mode control. In order to show the usefulness of the proposed method, prediction results of the proposed model are compared to those from the circuit level simulator, PSIM.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.5
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• pp.62-70
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• 2007

In this paper, the boost Power Factor Correction(PFC) technique for Direct Torque Control(DTC) of brushless DC motor drive in the constant torque region is implemented on a TMS320F2812DSP. Unlike conventional six-step PWM current control, by properly selecting the inverter voltage space vectors of the two-phase conduction mode from a simple look-up table at a predefined sampling time, the desired quasi-square wave current is obtained, therefore a much faster torque response is achieved compared to conventional current control. Furthermore, to eliminate the low-frequency torque oscillations caused by the non-ideal trapezoidal shape of the actual back-EMF waveform of the BLDC motor, a pre-stored back-EMF versus position look-up table is designed. The duty cycle of the boost converter is determined by a control algorithm based on the input voltage, output voltage which is the dc-link of the BLDC motor drive, and inductor current using average current control method with input voltage feed-forward compensation during each sampling period of the drive system. With the emergence of high-speed digital signal processors(DSPs), both PFC and simple DTC algorithms can be executed during a single sampling period of the BLDC motor drive. In the proposed method, since no PWM algorithm is required for DTC or BLDC motor drive, only one PWM output for the boost converter with 80 kHz switching frequency is used in a TMS320F2812 DSP. The validity and effectiveness of the proposed DTC of BLDC motor drive scheme with PFC are verified through the experimental results. The test results verify that the proposed PFC for DTC of BLDC motor drive improves power factor considerably from 0.77 to as close as 0.9997 with and without load conditions.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.5
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• pp.1325-1331
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• 1996

In this paper, a new current-memory circuit is proposed that reduces the clock feedthrough(CFT) error voltage causing total harmonic distortion(THD) increment in switched-current(SI) systems. Using PMOS transistor in CMOS complementary, the proposed one reduces output distortion current due to the CFT errorvoltage. A proposed current-memory is designed using a 1.2.mu.m CMOS process anda 1MHz sinusoidal signal having a 68.mu.A amplitude current is applied as input (sampling frequency:20MHz). It hasbeen shown from the simulation that the output distortion current effected by the CFT error voltage is reduced by approximately 10 times the error voltage of conventional one, THD is -57dB in case ofappling 1kHz frequency input signalwith 0.5 peak signal-to-bias current ratio.