• ETRI Journal
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• v.28 no.4
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• pp.486-494
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• 2006

Two current-mode and/or voltage-mode quadrature oscillator circuits each using one fully-differential second-generation current conveyor (FDCCII), two grounded capacitors, and two (or three) grounded resistors are presented. In the proposed circuits, the current-mode quadrature signals have the advantage of high-output impedance. The oscillation conditions and oscillation frequencies are orthogonally (or independently) controllable. The current-mode and voltage-mode quadrature signals can be simultaneously obtained from the second proposed circuit. The use of only grounded capacitors and resistors makes the proposed circuits ideal for integrated circuit implementation. Simulation results are also included.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.11
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• pp.56-65
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• 1997

In this paper, a design of current-mode continuous-time filters for low voltage and high frequency applictions using complementary bipolar current mirror paris is presented. The proposed current-mode filters consist of simple bipolar current mirrors and capacitors and are quite suitable for monolithic integrtion. Since the design method of the proposed curent-mode filters is based on the integrator type of realization, it can be used for a wide range of applications. And the cutoff frequency of th efilters can be easily changed by the DC cntrolling current. As design examples, the 5th order butterworth filters are designed by cascade and leapfrog methods with tunable cutoff frequencies from 30MHz to 100MHz. The characteristics of the designed current mode filters are simulated and examined by SPICE using standard bipolar transistor parameters.

• Journal of Power Electronics
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• v.11 no.1
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• pp.59-63
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• 2011

This paper presents the modeling of the sampling effect in the p-type average current mode control. The prediction of the high frequency components near half of the switching frequency in the current loop gain is given for the p-type average current mode control. By the proposed model, the prediction accuracy is improved when compared to that of conventional models. The proposed method is applied to a buck converter, and then the measurement results are analyzed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.37-43
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• 2008

This paper introduces a high-speed low-power self-timed current-mode logic (STCML) that reduces both dynamic and leakage power dissipation. STCML significantly reduces the leakage portion of the power consumption using a pulse-mode control for shorting the virtual ground node. The proposed logic style also minimizes the dynamic portion of the power consumption due to short-circuit current by employing an enhanced self-timing buffer. Comparison results using a 80-nm CMOS technology show that STCML achieves 26 times reduction on leakage power consumption and 27% reduction on dynamic power consumption as compared to the conventional current-mode logic. They also indicate that up to 59% reduction on leakage power consumption compared to differential cascode voltage switch logic (DCVS).

• Journal of Electrical Engineering and Technology
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• v.10 no.5
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• pp.1989-2000
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• 2015

In this paper, digital peak current mode control for single phase H-bridge inverters is developed and implemented. The digital peak current mode control is achieved by directly controlling the PWM signals by cycle-by-cycle current limitation. Unlike the DC-DC converter where the output voltage always remains in the positive region, the output of DC-AC inverter flips from positive to negative region continuously. Therefore, when the inverter operates in negative region, the control should be changed to valley current mode control. Thus, a novel control logic circuit is required for the function and need to be analyzed for the hardware to track the sinusoidal reference in both regions. The problem of sub-harmonic instability which is inherent with peak current mode control is also addressed, and then proposes the digital slope compensation in constant-sloped external ramp to suppress the oscillation. For unipolar PWM switching method, an adaptive slope compensation in digital manner is also proposed. In this paper, the operating principles and design guidelines of the proposed scheme are presented, along with the performance analysis and numerical simulation. Also, a 200W inverter hardware prototype has been implemented for experimental verification of the proposed controller scheme.

• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.3
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• pp.219-225
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• 2005

In this paper, a new discrete-time small signal model of an average current mode control is proposed to predict the inductor current responses. Compared to the peak current mode control, the analysis of the average current mode control is difficult because of its presence of an compensation network. By utilizing sampler model, a new discrete-time small signal model is derived and used to predict the behaviors of an inductor current of average current mode control employing generalized compensation networks. In order to show the usefulness of the proposed model, prediction results of the proposed model are compared to those of the circuit level simulator, PSIM and experiment.

• Progress in Superconductivity and Cryogenics
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• v.14 no.3
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• pp.23-27
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• 2012

This paper aims to evaluate the feasibility of using no-insulation High Temperature Superconducting (HTS) coil in persistent current mode system. A HTS coil in persistent current mode system usually includes one or more non-superconducting joints in its circuit. And the current decaying rate of the coil is affected by the resistance of joint in persistent current circuit. If the resistance of joint is large, decaying rate of the current drastically increases. Therefore, reducing the joint resistance of the HTS coil is very important in persistent current mode system. In this paper, the no-insulation HTS coil is suggested as a way to reduce the joint resistance with the embedded parallel contact resistance naturally made by no-insulation winding method. Two small coils are fabricated with insulation and no-insulation winding method, and persistent current mode system experiment of each coil is preformed and analyzed.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.10
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• pp.1477-1483
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• 2013

This paper proposes a low-voltage current-mode integrator for a continuous-time current-mode baseband channel selection filter. The low-voltage current-mode linear cascode integrator is introduced to offer advantages of high current gain and improved unity-gain frequency. The proposed current-mode integrator has fully differential input and output structure consisting of CMOS complementary circuit. Additional cascode transistors which are operated in linear region are inserted for bias to achieve the low-voltage feature. Frequency range is also controllable by selecting proper bias voltage. From simulation results, it can be noticed that the implemented integrator achieves design specification such as low-voltage operation, current gain, and unity gain frequency.

• Progress in Superconductivity and Cryogenics
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• v.12 no.1
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• pp.56-60
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• 2010

Recently, many researches have been carried out for a high temperature superconducting (HTS) magnet which is advantageous in high critical current density and critical temperature. In HTS magnet, however, critical current is decreased by perpendicular magnetic field and persistent current is hard to maintain due to a low index value and high joint resistance compared with low temperature superconducting (LTS) magnet. In this paper, the HTS magnet using BSCCO wire was simulated through finite element method (FEM) and manufactured. we experimentally investigated operating characteristics of the compensating mode of the HTS magnet for current decay and made a comparison between persistent current mode and compensating mode. A feedback control unit was used to sustain current within specified ranges with defined upper and lower limits.

• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.2
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• pp.134-137
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• 2019

A wide-bandwidth current controller is required for fast charging/discharging of super capacitor applications. Peak current mode is generally used to accomplish fast charging/discharging because this mode has fast response characteristics. However, the peak current mode control must have a slope compensation function to restrain sub-harmonics oscillation. The slope must be changed accordingly if the controlled output voltage is varied. However, changing the slope for every changed output voltage is not easy. The other solution, selecting the slope as the maximum value, causes a slow response problem to occur. Therefore, we propose a hybrid mode controller that uses a peak current and a newly specified valley current. Through the proposed hybrid mode control, the sub-harmonic oscillation does not occur when the duty is larger than 0.5 because of the fast response.