• Journal of Aerospace System Engineering
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• v.14 no.6
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• pp.79-84
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• 2020

Cooler driver electronics (CDE) for maintaining low temperature of the satellite payload IR sensor consists of a compressor that has a pulsation current load condition when it is operated. This pulsation current produces large voltage fluctuation, which affects both load and regulated bus stability. Thus, CDE power conditioning system consists of a primary bus, infrared power distribution unit for battery charging and protection, reverse current protection diode, and battery, which is used as a buffer. In this study, the operational mode analysis is performed by each part with equivalent impedance modeling verified through system level simulation. From this mode analysis, the safety margin for state of charge and open circuit voltage of the battery is determined for satisfying the minimum operational voltage of the CDE load.

• Proceedings of the KIEE Conference
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• 1994.07a
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• pp.539-541
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• 1994

The average current mode control of zero current switched series resonant converter is proposed. The conventional current controllers such as bang bang current controller and predictive current cantroller have some demerits like current offset and complexity. In this paper, the proposed current control technique are conventional current control techniques are comparatively studied. By the proposed control technique. the current cantroller can be simplely implemented without current offset.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.292-300
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• 2015

This paper proposes a high-efficiency, dual-mode PWM / linear buck converter with a wide-input range. The proposed converter was designed with a mode selector that can change the operation between PWM / linear mode by sensing a load current. The proposed converter operates in a linear mode during a light load and in PWM mode during a heavy load condition in order to ensure high efficiency. In addition, the mode selector uses a bit counter and a transmission gate designed to protect from a malfunction due to noise or a time-delay. Also, in conditions between $-40^{\circ}C$ and $140^{\circ}C$, the converter has variations in temperature of $0.5mV/^{\circ}C$ in the PWM mode and of $0.24mV/^{\circ}C$ in the linear mode. Also, to prevent malfunction and breakdown of the IC due to static electricity, the reliability of IC was improved by embedding a self-produced 8 kV-class(Chip level) ESD protection circuit of a P-substrate Triggered SCR type with high robustness characteristics.

• Journal of information and communication convergence engineering
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• v.7 no.3
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• pp.263-267
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• 2009

Cylindrical monopole antenna is one of most promising candidates for multi-band applications such as PCS, WLAN, DMB, and UWB wireless services. In this research, we demonstrate that there exist two types of current distributions according to the exciting frequency in a double band cylindrical monopole antenna, in which double resonance is achieved by adjusting the coupling structure of the antenna base. The operating modes of current distributions are identified from CST software simulations, the standing wave mode in a lower band and the traveling wave mode in a higher band. Also it is noticed that the mode behavior is quite similar to a helical antenna, a standing-wave (resonance) mode and a traveling-wave (non-resonance) mode according to the electrical dimensions of antenna. The effective ranges for operating modes and design formulas of the double band antenna are derived from simulation and measured results.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.5
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• pp.794-803
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• 1987

In this paper, the SPICE 2.G6 JFET subroutine and other related subroutines are modified for circuit simulation of GaAs MESFET IC's. The hyperbolic tangent model is used for the drain current-voltage characteristics of GaAs MESFET's and derived channel-conductance and drain-conductance model from the above current model are implemented into small-signal model of GaAs MESFET's. And, device capacitance model which consider after-pinch-off state are modified, and device charge model for SPICE 2G.6 are proposed. The result of modification is shown to be suitable for GaAs circuit simulator, showing good agreement with experimetal results. Forthermore the DC convergence of this paper is better than that of SPICE 2.G JFET subroutine. GaAs MESFET model in this paper is applied for both depletion mode GaAs MESFET and enhancement-mode GaAs MESFET without difficulty.

• Electrical & Electronic Materials
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• v.10 no.6
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• pp.562-569
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• 1997

The resonance characteristics on vibration mode of a transverse type ceramic resonator and the output voltage characteristics of a piezoelectric ceramic transformer are discussed in the effects of partial electrode arrangement (one sided, centered and both sided). A resonance characteristics of resonator depended strongly on both a vibration mode and a electrode structure because of a strain distribution. The maximum resonance current of a piezoelectric ceramic transformer [PCT] with partial centered electrode appeared in λ/2 mode, and that of a PCT with partial both sided electrode appeared in 3λ/2 mode. But the maximum output voltage of those samples appeared in λ/2 mode. In the PCT with partial both sided electrode, the ration of output voltage to input current was highest out of all samples and the poling voltage was a half times of 깬두 type transformer.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.19-26
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• 2005

We have studied the relationship between static mode behavior and dynamic characteristics of multiple transverse-mode VCSELs by measuring the modal L-I and I-V characteristics. Dependence of the resonance frequencies of RIN (relative intensity noise) spectra on the injection current can be understood by modal L-I characteristics and mode-coupling effects. Each transverse mode behaves as an independent diode laser with the different threshold current in large active-area VCSELs, and the multiple-step turn-on is observed when step-current input is applied. This multiple-step turn-on is a result of different turn-on delay times of the transverse modes. Since the multiple-step turn-on increases the rise-time significantly, the wide active-area VCSELs are not suitable for high-speed optical transmitters unless the input current is adjusted for single transverse-mode operation.

• Journal of Electrical Engineering and Technology
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• v.9 no.1
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• pp.301-306
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• 2014

We proposed a new PCB-type 'common-mode current($I_c$) and differential-mode current($I_d$) detector' working for fast detection of $I_c$ and $I_d$ from the differential-mode signaling, with miniaturization effect and possibility of cheaper fabrication. In order to realize this device, we suggest a branch-line-coupler balun having a composite right- and left-handed(CRLH) one-layer microstrip phase-shifting line as compact as roughly ${\lambda}_g/14$. The presented balun obviously is different from the conventional bent-&-folded delay lines or slits on the ground for coupling the lines on the top and bottom dielectrics. As we connect the suggested balun output ports of the differential-mode signal lines via the through-port named U and coupled-port named L, $I_c$ and $I_d$ will appear at port ${\Delta}$ and port ${\Sigma}$ of the present device, in order. The validity of the design scheme is verified by the circuit-and numerical electromagnetic analyses, and the dispersion curve proving the metamaterial characteristics of the geometry. Besides, the examples of the $I_c$ and $I_d$ indicator are observed as the even and odd modes in differential-mode signal feeding. Also, the proposed device is shown to be very compact, compared with the conventional structure.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.79-85
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• 2009

The design of a 3.2 Gb/s serial link receiver in $0.18{\mu}m$ CMOS process is presented. The major factors limiting the performance of high-speed links are transmission channel bandwidth, timing uncertainty. The design uses a multi-level signaling(4-PAM) to overcome these problems. Moreover, to increase data bit-rate and lower BER, we designed this circuit by using a current mode amplifier, Current-mode Logic(CML) sampling latches. The 4-PAM receiver achieves 3.2 Gb/s and BER is less than $1.0\;{\times}\;10^{-12}$. The $0.5\;{\times}\;0.6\;mm^2$ chip consumes 49 mA at 3.2 Gb/s from a 1.8-V supply.

• Journal of IKEEE
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• v.17 no.1
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• pp.77-82
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• 2013

In this paper, dc-dc buck converter controled by the peak current-mode pulse-width-modulation (PWM) presented. Based on the small-signal model, we propose the novel methods of the power stage and the systematic stability designs. To improve the reliability and performance, over-temperature and over-current protection circuits have been designed in the dc-dc converter systems. To prevent electrostatic An electrostatic discharge (ESD) protection circuit is proposed. The proposed dc-dc converter circuit exhibits low triggering voltage by using the gate-substrate biasing techniques. Throughout the circuit simulation, it confirms that the proposed ESD protection circuit has lower triggering voltage(4.1V) than that of conventional ggNMOS (8.2V). The circuit simulation is performed by Mathlab and HSPICE programs utilizing the 0.35um BCD (Bipolar-CMOS-DMOS) process parameters.