• Journal of Electrical Engineering and Technology
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• 제13권6호
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• pp.2301-2309
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• 2018

In a field-oriented vector-controlled permanent magnet synchronous motor (PMSM) control system, the d-axis current control loop can offer a free degree of freedom which can be used to improve control performances. However, in the industry the desired d-axis current command is usually set as zero without using the free degree of freedom. This paper proposes a method to use the degree of freedom for control performance improvement. It is assumed that both the inner loop proportional-integral (PI) current controller and the q-axis outer loop PI speed controller are tuned by the well-known tuning rules. This paper gives an optimal d-axis reference current command generator such that some useful performance indexes are minimized and/or a tradeoff between conflicting performance criteria is made. This paper uses a differential evolution algorithm to autotune the parameter values of the optimal d-axis reference current command generator. This paper implements the proposed control system in real time on a Texas Instruments TMS320F28335 floating-point DSP. This paper also gives experimental results showing the practicality and feasibility of the proposed control system, along with simulation results.

• Journal of Power Electronics
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• 제13권5호
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• pp.829-840
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• 2013

The modified sinusoidal pulse-width modulation (SPWM) is one of the PWM techniques used in three-phase AC-DC buck converters. The modified SPWM works without the current sensor (the converter is current sensorless), improves production of sinusoidal AC current, enables obtainment of near-unity power factor, and controls output voltage through modulation gain (ranging from 0 to 1). The main problem of the modified SPWM is the huge starting current and voltage (during transient) that results from a large step change from the reference voltage. When the load changes, the output voltage significantly drops (through switching losses and non-ideal converter elements). The single-input single-output (SISO) approach with minor-loop voltage feedback controller presented here overcomes this problem. This approach is created on a theoretical linear model and verified by discrete-model simulation on MATLAB/Simulink. The capability and effectiveness of the SISO approach in compensating start-up current/voltage and in achieving zero steady-state error were tested for transient cases with step-changed load and step-changed reference voltage for linear and non-linear loads. Tests were done to analyze the transient performance against various controller gains. An experiment prototype was also developed for verification.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 추계학술대회 논문집 Vol.18
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• pp.159-160
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• 2005

The superconducting fault current limiter(SFCLs) provides the effect such as enhancement in the power system reliability due to limiting fault current in a few miliseconds. The Flux-lock type SFCL using the YBCO film among various type SFCLs consists of the primary and the secondary copper coils that are wound in parallel each other through the iron core. The operation can be controlled by adjusting the inductances and the winging directions of each the coil. We compared the current limiting performance on the additive and the subtractive polarity winding directions in case of an open-loop iron core. To analyze quench characteristics, we experimented various phase angle.

• Journal of Power Electronics
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• 제12권4호
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• pp.595-603
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• 2012

This paper presents a full digital control strategy for parallel connected modular inverter systems. Each modular inverter is a high frequency (HF) AC link inverter which is composed of a HF inverter and a HF transformer followed by a cycloconverter. To achieve equal sharing of the load current and to suppress the circulating currents among the modules, a three-loop control strategy, consisting of a common output voltage regulation (OVR) loop, individual circulating current suppression (CCS) loops and individual inner current tracking (ICT) loops, is proposed. The ICT loops are implemented with predictive current control from which high precision current tracking can be obtained. The effectiveness of the proposed control strategy is verified by simulation and experimental results from parallel connected two full-bridge HF AC link inverter modules.

• 전력전자학회:학술대회논문집
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• 전력전자학회 1998년도 전력전자학술대회 논문집
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• pp.275-278
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• 1998

The mathematical interpretation of a practical sampler which is useful to obtain the small signal models for the peak and average current mode controls is proposed. Due to the difficulties in applying the Shannon's sampling theorem to the analysis of sampling effects embedded in the current mode control, several different approaches have been reported. However, these approaches require the information of the inductor current in a discrete expression, which restricts the application of the reported method only to the peak current mode control. In this paper, the mathematical expressions of sampling effects on a current loop which can directly apply the Shannon's sampling theorem are newly proposed, and applied to the modeling of the peak current mode control. By the newly derived models of a practical sampler, the models in a discrete time domain and a continuous time domain are obtained. It is expected that the derived models are useful for the control loop design of power supplies. The effectiveness of the derived models are verified through the simulation and experimental results.

• 한국정보통신학회논문지
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• 제21권11호
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• pp.2009-2014
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• 2017

본 논문에서는 변화하는 루프필터 전압을 시정수 비교기를 사용하여 감지하고, 이의 출력에 따라 루프필터 전압변화를 보상하여 단일 칩으로 구현이 가능한 작은 크기의 위상고정루프를 제안하였다. 제안된 위상고정루프는 기존 구조에서는 안전한 동작이 불가능한 크기인 작은 용량을 가지는 커패시터를 사용하여 칩의 크기를 최소화 하였다. 시정수 비교기는 작은 시정수 값을 가지는 저항, 커패시터와 높은 시정수 값을 가지는 저항, 커패시터를 통과한 신호들을 입력으로 받아 루프필터 출력 전압의 변화를 감지한다. 시정수가 큰 노드의 출력은 루프필터 출력전압의 평균 값을 가지고, 시정수가 작은 노드의 출력은 루프필터 출력전압과 거의 같은 값을 가진다. 각 노드의 차이를 비교하여 나온 출력은 전류 보상기를 제어하여 작은 크기의 루프필터 커패시터를 충 방전 시킨다. 이는 제안된 위상고정루프를 안정하게 동작하도록 한다. 제안된 위상고정루프는 1.8V $0.18{\mu}m$ CMOS 공정을 사용하여 설계하였고, Hspice 시뮬레이션을 통해 회로의 동작을 검증하였다.

• Journal of information and communication convergence engineering
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• 제3권1호
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• pp.18-22
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• 2005

This paper presents the analog adaptive phase-locked loop (PLL) architecture with a new adaptive bandwidth controller to reduce locking time and minimize jitter in PLL output for wireless communication. It adaptively controls the loop bandwidth according to the locking status. When the phase error is large, the PLL increases the loop bandwidth and reduces locking time. When the phase error is small, the PLL decreases the loop bandwidth and minimizes output jitters. The adaptive bandwidth control is implemented by controlling charge pump current depending on the locking status. A 1.28-GHz CMOS phase-locked loop with adaptive bandwidth control is designed with 0.35 $mu$m CMOS technology. It is simulated by HSPICE and achieves the primary reference sidebands at the output of the VCO are approximately -80dBc.

• Journal of information and communication convergence engineering
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• 제19권2호
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• pp.84-92
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• 2021

The research on waste power batteries in China in the past ten years reveals that the power battery recycling industry is enormous but marred with several challenges. A study of China's current power battery closed-loop supply chain revealed some issues in the power battery recycling industry, such as imperfect supply chain, small recycling scale, asymmetric information, and imperfect profit distribution mechanism. This paper uses the theory of corporate social responsibility and consumer choice to propose a closed-loop network of power batteries based on block chain technology and analyzes the existing closed-loop supply chain of power batteries. Consequently, this study provides a new idea for developing the power battery closed-loop supply chain by proposing the closed-loop network of power batteries based on blockchain technology.

• Journal of Electrical Engineering and Technology
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• 제12권4호
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• pp.1529-1536
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• 2017

A digital dual-channel interleaved phase-shift full-bridge converter is investigated in this paper, and its topology and principle are analyzed. To realize current sharing and stabilize the output voltage, a controller with current sharing loop and closed voltage loop is employed. In addition, current sharing will increase the output current fluctuation and a new digital interleaved driving technology is proposed to reduce the output current ripple. To verify the analysis, simulation and experiments are carried out, which shows the effectiveness of the proposed control strategies.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 추계학술대회 논문집 전력기술부문
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• pp.368-370
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• 2005

Superconducting fault current limiter (SFCL) provides the effect such as enhancement in power system reliability due to limiting fault current in a few miliseconds. The flux-lock type SFCL among various type SFCLs consists of two coils wound on the same iron core and a component using the YBCO thin film. In the SFCL, operation characteristics can be controlled by adjusting the inductances and the winding directions of the coils. In this paper, we investigated the various fault current limiting characteristics according to the voltage level. To analyze the current limiting performance, we compared operational characteristics on the subtractive polarity winding direction on in case of open-loop iron core.