• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.5 s.347
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• pp.35-44
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• 2006

Reflective semiconductor optical amplifiers(R-SOAs) were designed with high gain, wide optical bandwidth, high thermal reliability and wide modulation bandwidth in TO-can package for the transmitter of wavelength division multiplexed-passive optical network(WDM-PON) application. Double trench structure and current block layer were introduced in designing the active layer of R-SOA to enable high speed modulation. The injection power requirement and the viable temperature range of WDM-PON system are experimentally analysed in based on Amplified Spontaneous Emission(ASE)-injected R-SOAs. The effect of the different injection spectrum in the gain-saturated R-SOA was experimentally characterized based on the measurements of excessive intensity noise, Q factor, and BER. The proposed spectral pre-composition method reduces the bandwidth of injection source below the AWG bandwidth and thereby avoids spectrum distortion impeding the intensity noise reduction originated from the amplitude squeezing.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.65-73
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• 2006

This work presents a 14b 200KS/s $0.87mm^2$ 1.2mW 0.18um CMOS algorithmic A/D converter (ADC) for intelligent sensors control systems, battery-powered system applications simultaneously requiring high resolution, low power, and small area. The proposed algorithmic ADC not using a conventional sample-and-hold amplifier employs efficient switched-bias power-reduction techniques in analog circuits, a clock selective sampling-capacitor switching in the multiplying D/A converter, and ultra low-power on-chip current and voltage references to optimize sampling rate, resolution, power consumption, and chip area. The prototype ADC implemented in a 0.18um 1P6M CMOS process shows a measured DNL and INL of maximum 0.98LSB and 15.72LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 54dB and 69dB, respectively, and a power consumption of 1.2mW at 200KS/s and 1.8V. The occupied active die area is $0.87mm^2$.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.6
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• pp.715-720
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• 2016

This paper proposes a PWM (Pulse Width Modulation) voltage mode DC-DC step-up converter for portable devices. The converter, which is operated with a 1 MHz switching frequency, is capable of reducing the mounting area of passive devices, such as inductor and capacitor, and is suitable for compact mobile products. This step-up converter consists of a power stage and a control block. The circuit elements of the power stage are an inductor, output capacitor, MOS transistors Meanwhile, control block consist of OPAMP (operational amplifier), BGR (band gap reference), soft-start, hysteresis comparator, and non-overlap driver and some protection circuits (OVP, TSD, UVLO). The hysteresis comparator and non-overlapping drivers reduce the output ripple and the effects of noise to improve safety. The proposed step-up converter was designed and verified in Magnachip/Hynix 0.18um 1-poly, 6-metal CMOS process technology. The output voltage was 5 V with a 3.3 V input voltage, output current of 100 mA, output ripple less than 1% of the output voltage, and a switching frequency of 1 MHz. These designed DC-DC step-up converters could be applied to the Personal Digital Assistants(PDA), cellular Phones, Laptop Computer, etc.

• Journal of Sensor Science and Technology
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• v.10 no.3
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• pp.148-155
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• 2001

A pressure sensor on the tip of a catheter which is utilized to measure the in-vivo pressure in a human body was fabricated and the characteristic of the pressure sensor as measured. To fit into a catheter with 1 mm caliber, samples of $150\;{\mu}m$(thickness) ${\times}$ (600, 700, 800, 900, 1000) ${\mu}m$(width) ${\times}2\;mm$(length) was fabricated. The thicker face with $450\;{\mu}m$ thickness of SDB wafer was made thin to $134\;{\mu}m$ thickness using KOH etchant and it made possible to fabricate sensor cell with the width shorter than 1 mm. Different to the whitstone bridge sensor, we formed one piezoresistor and one reference resistor in sensor. Therefore there are possibilities of reduction of the sensitivity, then by using the simulation tool ANSYS 5.5.1, the location and the type of the piezoresistor was optimized. Another piezoresistor type of sensor which contain one longitudinal and one transverse piezoresistor was fabricated at the same time, but the sensitivity was not improved very much. To get the output versus the pressure, a constant current source and a implementation amplifier was used. As a result, the maximum sensitivity of the sensor with one piezoresistor was $1.6\;{\mu}V/V/mmHg$.

• Journal of IKEEE
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• v.2 no.2 s.3
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• pp.278-284
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• 1998

This paper describes a l0b CMOS A/D converter (ADC) for HDTV applications. The proposed ADC adopts a typical multi-step pipelined architecture. The proposed circuit design techniques are as fo1lows: A selective channel-length adjustment technique for a bias circuit minimizes the mismatch of the bias current due to the short channel effect by supply voltage variations. A power reduction technique for a high-speed two-stage operational amplifier decreases the power consumption of amplifiers with wide bandwidths by turning on and off bias currents in the suggested sequence. A typical capacitor scaling technique optimizes the chip area and power dissipation of the ADC. The proposed ADC is designed and fabricated in s 0.8 um double-poly double-metal n-well CMOS technology. The measured differential and integral nonlinearities of the prototype ADC show less than ${\pm}0.6LSB\;and\;{\pm}2.0LSB$, respectively. The typical ADC power consumption is 119 mW at 3 V with a 40 MHz sampling rate, and 320 mW at 5 V with a 50 MHz sampling rate.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.9 no.2
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• pp.58-67
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• 1995

The paper describes the variation of magnetic fields caused by the operation of induction motors. The measuring system consists of the self-integrating magnetic field sensor, amplifier, and active integrator. From the calibration experiments, the frequency bandwidth of the magnetic field measuring system ranges from 20[Hz] to 300[kHz] and sensitivity is 0.234(mV/$\mu\textrm{T}$]. The magnetic fields generated under steady state and starting operations of duction motor are recorded by the proposed measuring system, and the fast Fourier transformation(FFT) of the measured data is performed to analyze the harmonic components. A single pulsed magnetic field is strongly caused by direct starting the induction motor, and its peak value is greater than 5 times as compared with the steady state value. The long transient duration and high intensity originates from the large inductance and dynamic characteristic of the induction motor, During the steady state operation of induction motor, subharmonics of magnetic field components, which depend on the pole number of induction motor, are observed. The lower order power-line harmonics can be inferred from the voltage flicker and current ripple which are derived from the torque fluctuation of induction motor. In the case of the induction motor drived by inverter, the harmonics of magnetic field are much more than those caused by direct starting method and are found generally to increase with decreasing the driving frequency.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.10
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• pp.1-11
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• 1998

This paper presents a new implementation method of the pulsed NMR(nuclear magnetic resonance) apparatus, which contains a single coil in a magnet console, to detect a NMR signal. Applying an RF magnetic field of 5MHz to the magnet console which is designed to have Larmor frequency of 5MHz for hydrogen atom, the hydrogen NMR signal was obtained from the glycerin which was put in the magnet console as a sample. The DC magnetic field in the magnet console was implemented with a permanent magnet of 1168 gauss and the RF magnetic field was generated appling an RF signal with the frequency of 5MHz and the current magnitude of 8A to a coil of 5.73${\mu}$H. The magnitude of the NMR signal was maximum when the RF magnetic field was generated for 2.8 ${\mu}$sec, and the period of generating the RF magnetic field was designed to 100msec for detecting the NMR signal repeatedly. The NMR signal, radiated from the sample in the magnetic console, was appeared as an amplitude-modulated signal with a frequency equal to the Larmor frequency. The signal, induced in the coil, was amplified in the tx/rx separation circuit, preamplifier and intermediate amplifier by a factor of 20.7dB, 36dB and 40dB, respectively, and the signal was detected by a synchronous detection circuits, then the NMR signal was obtained.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.77-85
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• 2008

This work proposes a 12b 130MS/s 108mW $1.8mm^2$ 0.18um CMOS ADC for high-quality video systems such as TFT-LCD displays and digital TVs requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC optimizes power consumption and chip area at the target resolution and sampling rate based on a three-step pipeline architecture. The input SHA with gate-bootstrapped sampling switches and a properly controlled trans-conductance ratio of two amplifier stages achieves a high gain and phase margin for 12b input accuracy at the Nyquist frequency. A signal-insensitive 3D-fully symmetric layout reduces a capacitor and device mismatch of two MDACs. The proposed supply- and temperature- insensitive current and voltage references are implemented on chip with a small number of transistors. The prototype ADC in a 0.18um 1P6M CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 2.12LSB, respectively. The ADC shows a maximum SNDR of 53dB and 51dB and a maximum SFDR of 68dB and 66dB at 120MS/s and 130MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 108mW at 130MS/s and 1.8V.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.2
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• pp.168-175
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• 2017

In this paper, a 5V small-area NMOS-diode eFuse OTP memory cell is proposed. This cell which is used in PMICs consists of a 5V NMOS transistor and an eFuse link as a memory part, based on a BCD process. Also, a regulated voltage of V2V ($=2.0V{\pm}10%$) instead of the conventional VDD is used to the pull-up loads of a VREF circuit and a BL S/A circuit to obtain a wider operational voltage range of the eFuse memory cell. When this proposed cells are used in the simulation, their sensing resistances are found to be $15.9k{\Omega}$ and $32.9k{\Omega}$, in the normal read mode and in the program-verify-read mode, respectively. Furthermore, the read current flowing through a non-blown eFuse is restricted to $97.7{\mu}A$. Thus, the eFuse link of a non-blown eFuse OTP memory cell is kept non-blown. The layout area of the designed 1kb eFuse OTP memory IP based on Dongbu HiTek's BCD process is $168.39{\mu}m{\times}479.45{\mu}m(=0.08mm^2)$.