• Journal of Power Electronics
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• v.5 no.2
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• pp.104-108
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• 2005

This paper presents the performance improvement of voltage-mode controlled interleaved synchronous buck converters. This is a voltage-mode controlled scheme, where the controllers do not need an external saw-tooth generator for PWM generation and the loop design is easier. The controller implementation requires only a single error amplifier and gives almost current mode control performance. The control scheme uses voltage feedback with two loops similar to current mode control: one for the slow outer loop and the other for the faster inner PWM control loop. To improve the performance of the converter system a coupled inductor is used. This coupled inductor reduces the magnetic size and also improves the converter's transient performance without increasing the steady-state current ripple. The effectiveness of the proposed control scheme is demonstrated through PSIM simulations.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1030-1033
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• 2002

This paper, a new simple controller operates in continuous conduction mode (CCM) for Boost power factor collection converter is introduced. The duty ratios are obtained by comparisons of a sensed signal from inductor current and a negative ramp carrier waveform in each switching period. By using the proposed controller, input voltage sensing, error amplifier in the current feedback loop, and analog multiplier／divider are not required, then, the control circuit implementation is very simple. To verify the proposed controller, the circuit simulation for Boost power factor correction converter was applied. For the results, the input current waveform was shaped to be closely sinusoidal, implying low THD.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.815-818
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• 2003

New sensing and writing schemes for a magneto-resistive random access memory (MRAM) with a twin cell structure are proposed. In order to enhance the cell reliability, a scheme of the low voltage precharge is employed to keep the magneto resistance (MR) ratio constant. Moreover, a common gate amplifier is utilized to provide sufficient voltage signal to the bit line sense amplifiers under the small MR ratio structures. To enhance the writing reliability, a current mode technique with tri-state current drivers is adopted. During write operations, the bit and /bit lines are connected. And 'HIGH' or 'LOW' data is determined in terms of the current direction flowing through the MTJ cell. With the viewpoint of the improved reliability of the cell behavior and sensing margin, HSPICE simulations proved the validity of the proposed schemes.

• Journal of Korean Vacuum Science & Technology
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• v.3 no.1
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• pp.59-65
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• 1999

There has been an interest to develop an efficient, compact microwave device using field-emitter-arrays (FEA)-based cathode. Toe valuate the optimum device-efficiency in a compact size, the propagation properties of the premodulated electron beam for the FEA-based cathode is studied in detail by the computer simulation using a PIC code, MAGIC. For the premodulated electron beam whose phase of the energy leads the phase of the current by $\pi$/2, the amplitude of the downstream current modulation can be kept as high as the initial modulation level. Using the beam parameters with the beam voltage of 6kV and the current of 2.0A, 30% of efficiency is predicted when the quality factor of 800 is chosen. the device length is reduced about twice compared with that of the conventional device. The design of practical planar cathode is carried out to meet the minimum diameter of the electron beam as 0.5 mm.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.2
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• pp.363-368
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• 2009

In the paper, we confirmed improvement Noise figure of the entire RF front-end using spiral inductor with PGS(Patterned Ground Shield) and current bleeding techniques. LNA design is to achieve simultaneous noise and input matching. Spiral inductor in input circuit of LNA inserted PGS for betterment of Q-factor. we modeling inductor using EM simulator, so compared with inductor of TSMC 0.18um. We designed and simulation the optimum structure of PGS using Taguchi's method. We confirmed enhancement of noise figure at LNA after substituted for inductor with PGS. Mixer designed using current bleeding techniques for reduced noise. We designed LNA using inductor with PGS and Mixer using current bleeding techniques, so confirmed improvement of noise figure.

• ETRI Journal
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• v.28 no.3
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• pp.386-388
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• 2006

Monolithic SiGe heterojunction bipolar transistor (HBT) variable gain amplifiers (VGAs) with a feedforward configuration have been newly developed for 5 GHz applications. Two types of the feedforward VGAs have been made: one using a coupled-emitter resistor and the other using an HBT-based current source. At 5.2 GHz, both of the VGAs achieve a dynamic gain-control range of 23 dB with a control-voltage range from 0.4 to 2.6 V. The gain-tuning sensitivity is 90 mV/dB. At $V_{CTRL}$= 2.4 V, the 1 dB compression output power, $P_{1-dB}$, and dc bias current are 0 dBm and 59 mA in a VGA with an emitter resistor and -1.8 dBm and 71mA in a VGA with a constant current source, respectively.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.949-952
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• 2000

A low power 10bit current-mode folding and interpolating CMOS analog to digital converter (ADC) with arithmetic folding blocks is presented in this paper. A current-mode two-level folding amplifier with a high folding rate (FR) is designed not only to prevent ADC from increasing a FR excessively, but also to perform a high resolution at a single power supply of 3.3V The proposed ADC is implemented by a 0.6${\mu}$m n-well CMOS single poly/double metal process. The simulation result shows a differential nonlinearity (DNL) of ${\pm}$0.5LSB, an integral nonlinearity (INL) of ${\pm}$1.0LSB

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.326-333
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• 2015

This paper reports an adaptive positive feedback bias control technique for operational transconductance amplifiers to adjust the bias current based on the output current monitored by a current replica circuit. This technique enables operational transconductance amplifiers to quickly adapt their power consumption to various analog workloads when they are configured with negative feedback. To prove the concept, a test voltage follower is fabricated in $0.5-{\mu}m$ CMOS technology. Measurement result shows that the power consumption of the test voltage follower is approximately linearly proportional to the load capacitance, the signal frequency, and the signal amplitude for sinusoidal inputs as well as square pulses.

• Journal of the Korea Safety Management & Science
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• v.17 no.3
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• pp.363-370
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• 2015

In this paper, the control technique of the stepping motor using back electromotive force(B-EMF) without encoder is investigated. The stepping motor generally uses the rotary encoder to detect the rotor position. Since this method increases the cost and the motor configuration size, the new closed-loop control method applied for the B-EMF was implemented by using current detect circuit, AD-converter, and micro controller unit(MCU). The control loop of stepping motor became very simplified. The current change of stepping motor measured by the amplifier was measured and analyzed, when the missing step is occurred. Based on the data from current feedback, position errors were compensated and confirmed by using AD-converter.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.10
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• pp.1169-1176
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• 2010

The RF front-end for L1/L2 dual-band Global Positioning System(GPS) receiver is presented in this paper. The RF front-end(down-converter) using low IF architecture consists of a wideband low noise amplifier(LNA), a current mode logic(CML) frequency divider and a I/Q down-conversion mixer with a poly-phase filter for image rejection. The current bleeding technique is used in the LNA and mixer to obtain the high gain and solve the head-room problem. The common drain feedback is adopted for low noise amplifier to achieve the wideband input matching without inductors. The fabricated RF front-end using $0.18{\mu}m$ CMOS process shows a gain of 38 dB for L1 and 41 dB for L2 band. The measured IIP3 is -29 dBm in L1 band and -33 dBm in L2 band, The input return loss is less than -10 dB from 50 MHz to 3 GHz. The measured noise figure(NF) is 3.81 dB for L1 band and 3.71 dB for L2 band. The image rejection ratio is 36.5 dB. The chip size of RF front end is $1.2{\times}1.35mm^2$.