• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.48-53
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• 2008

In this paper, we developed the MMIC low noise amplifier using 100 nm metamorphic HEMTs technology in combination with coplanar circuit topology for 94 GHz applications. The $100nm\times60{\mu}m$ MHEMT devices for the MMIC LNA exhibited DC characteristics with a drain current density of 655 mA/mm, an extrinsic transconductance of 720 mS/mm. The current gain cutoff frequency $(f_T)$ and maximum oscillation frequency $(f_{max})$ were 195 GHz and 305 GHz, respectively. The realized MMIC LNA represented $S_{21}$ gain of 14.8 dB and noise figure of 4.6 dB at 94 GHz with an over-all chip size of $1.8mm\times1.48mm$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.23-29
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• 2011

A dB-linearity improved variable gain amplifier (VGA) for GPS receiver is presented. The Proposed dB-linear current generator has improved dB-linearity error of ${\pm}0.15$dB. The VGA for GPS is designed using proposed dB-linear current generator and composed of 3 stage amplifiers. The IF frequency is assumed as 4MHz and the linearity requirement of the VGA for GPS receiver is defined as 24dBm of IIP3 using cascaded IIP3 equation and the VGA satisfies 24dBm when minimum gain mode. The DC-offset voltage is eliminated using DC-offset cancelation loop. The gain range is from -8dB to 52dB and the dB-linearity error satisfies ${\pm}0.2$dB. The 3-dB frequency has range of 35MHz~106MHz for the gain range. The VGA is designed using 0.18${\mu}m$ CMOS process. The power consumption is 3mW with 1.8V supply voltage.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.2
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• pp.128-135
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• 2013

This letter presents the MISHFET with si-doped AlGaN/GaN heterostructure for power amplifier. The device grown on 6H-SiC(0001) substrate with a gate length of 180 nm has been fabricated. The fabricated device exhibited maximum drain current density of 837 mA/mm and peak transconductance of 177 mS/mm. A unity current gain cutoff frequency was 45.6 GHz and maximum frequency of oscillation was 46.5 GHz. The reported output power density was 1.54 W/mm and A PAE(Power Added Efficiency) was 40.24 % at 9.3 GHz.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.130-137
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• 2013

This paper presents analog front-end(AFE) circuits for bio-potential measurement. The proposed AFE is composed of IA(instrument amplifier), BPF(band-pass filter), VGA(variable gain amplifier) and SAR(successive approximation register) type ADC. The low gm(LGM) circuits with current division technique and Miller capacitance with high gain amplifier enable IA to implement on-chip AC-coupling without external passive components. Spilt capacitor array with capacitor division technique and asynchronous control make the 12-b ADC with low power consumption and small die area. The total current consumption of proposed AFE is 6.3uA at 1.8V.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.2
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• pp.220-223
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• 2016

This letter proposes a low noise amplifier which has low noise figure and high linearity simultaneously using a cascode structure with an additional transistor. The proposed structure minimizes the noise source by using optimizing transistor sizes and also improves linearity from the current bleeding technique. The device was fabricated in a $0.5{\mu}m$ GaAs pHEMT process and has noise figure of 1.1 dB, a voltage gain of 15.0 dB, an $OIP_3$ of 30.8 dBm and an input/output return loss of 11.6 dB/10.4 dB from 1.8 to 2.6 GHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.10
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• pp.61-66
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• 2007

A gain enhancement rail-to-rail buffer amplifier for liquid crystal display (LCD) source driver is proposed. An op-amp with extremely high gain is needed to decrease the offset voltage of the buffer amplifier. Cascoded floating current source and class-AB control block in the op-amp achieve a high voltage gain by reducing the channel length modulation effect in high voltage technologies. HSPICE simulation in $1\;{\mu}V$ 15 V CMOS process demonstrates that voltage gain is increased by 30 dB. The offset voltage is improved from 6.84 mV to $400\;{\mu}V$. Proposed op-amp is fabricated in an LCD source driver IC and overall system offset voltage is decreased by 2 mV.

• The Transactions of the Korean Institute of Power Electronics
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• v.14 no.1
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• pp.62-71
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• 2009

In this paper, an improved drive method of piezoelectric PZT stack actuator for micro-positioning system is proposed and the performances are evaluated. This type of amplifier is based on switching technology efficiently handling the arbitrary regenerative energy from the piezoelectric actuator. The conventional voltage-feedback control method has the THD of -32dB (${\approx}2.5%$) with 100mHz sinusoidal reference, which means that the positioning performance in linearity degrades due to the hysteretic relationship between actuator voltage and the displacement. This paper proposed an improved charge-controlling method, which utilizes differential information of charge reference instead of integrating the actuator's current. The current waveform has THD under -40dBV (=1%) and the displacement waveform nearly -52dB (${\approx}0.25%$), which means that the positioning performance is very excellent. Finally, another method of the displacement feedback control has better performance than the voltage method, however there exists a limitation in performance of the system.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1997.04a
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• pp.236-238
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• 1997

A cellular power amplifier using an APCVD(Atmospheric Pressure Chemical Vapor Deposition)-grown SiGe base HBT of ETRI has been designed with a linear simulation CAD. The Si/SiGe HBT with an emitter area of 2$\times$8${\mu}{\textrm}{m}$$^2$typically has a cutoff frequency(f$_{T}$) of 7.0 GHz and a maximum oscillation frequency(f$_{max}$) of 16.1 GHz with a pad de-embedding A packaged power Si/SiGe HBT with an emitter area of 2$\times$8$\times$80${\mu}{\textrm}{m}$$^2$typically shows a f$_{T}$ of 4.7 GHz and a f$_{max}$ of 7.1 GHz at a collector current (Ic) of 115 mA. The power amplifier exhibits a Forward transmission coefficient(S21) of 13.5 dB, an input and an output reflection coefficients of -42 dB and -45 dB respectively. Up to now the III-V compound semiconductor devices hale dominated microwave applications, however a rapid progress in Si-based technology make the advent of the Si/SiGe HBT which is promising in low to even higher microwave range because of lower cost and relatively higher reproducibility of a Si-based process.ess.ess.

• ETRI Journal
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• v.29 no.4
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• pp.421-429
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• 2007

This paper presents a direct-conversion CMOS transceiver for fully digital DS-UWB systems. The transceiver includes all of the radio building blocks, such as a T/R switch, a low noise amplifier, an I/Q demodulator, a low pass filter, a variable gain amplifier as a receiver, the same receiver blocks as a transmitter including a phase-locked loop (PLL), and a voltage controlled oscillator (VCO). A single-ended-to-differential converter is implemented in the down-conversion mixer and a differential-to-single-ended converter is implemented in the driver amplifier stage. The chip is fabricated on a 9.0 $mm^2$ die using standard 0.18 ${\mu}m$ CMOS technology and a 64-pin MicroLead Frame package. Experimental results show the total current consumption is 143 mA including the PLL and VCO. The chip has a 3.5 dB receiver gain flatness at the 660 MHz bandwidth. These results indicate that the architecture and circuits are adaptable to the implementation of a wideband, low-power, and high-speed wireless personal area network.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.4
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• pp.1-9
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• 2002

The distribution characteristics of data retention time for DRAM was studied in connection with the probability distribution of the cell parameters. Using the cell parameters and the transient characteristics of cell node voltage, data retention time was investigated. The activation energy for dielectric layer growth on cell capacitance, the recombination trap energy for leakage current in the junction depletion region, and the sensitivity characteristics of sense amplifier were used as the random variables to perform the Monte Carlo simulation, and the probability distributions of cell parameters and distribution characteristics of cumulative failure bit on data retention time in DRAM cells were calculated. we found that the sensitivity characteristics of sense amplifier strongly affected on the tail bit distribution of data retention time.