• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.1-10
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• 2008

In this paper, we describe a design of a 128bit MRAM based on a new switching architecture which is Local Field Switching(LFS). LFS uses a local magnetic field generated by the current flowing through an MTJ. This mode reduces the writing current since small current can induce large magnetic field because of close distance between MTJ and the current. It also improves the cell selectivity over using conventional MTJ architecture because it doesn't need a digit line for writing. The MRAM has 1-Transistor 1-Magnetic Tunnel Junction (IT-1MTJ) memory cell structure and uses a bidirectional write driver, a mid-point reference cell block and a current mode sense amplifier. CMOS emulation cell is adopted as an LFS-MTJ cell to verify the operation of the circuit without the MTJ process. The memory circuit is fabricated using a $0.18{\mu}m$ CMOS technology with six layers o) metal and tested on custom board.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.2
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• pp.97-105
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• 2016

Microcontrollers (MCUs) for endpoint smart sensor devices of internet-of-thing (IoT) are being implemented as system-on-chip (SoC) with on-chip instruction flash memory, in which user firmware is embedded. MCUs directly fetch binary code-based instructions through bit-line sense amplifier (S/A) integrated with on-chip flash memory. The S/A compares bit cell current with reference current to identify which data are programmed. The S/A in reading '0' (erased) cell data consumes a large sink current, which is greater than off-current for '1' (programmed) cell data. The main motivation of our approach is to reduce the number of accesses of erased cells by binary code level transformation. This paper proposes a built-in write/read path architecture using binary code inversion method based on hot-spot region detection of instruction code access to reduce sensing current in S/A. From the profiling result of instruction access patterns, hot-spot region of an original compiled binary code is conditionally inverted with the proposed bit-inversion techniques. The de-inversion hardware only consumes small logic current instead of analog sink current in S/A and it is integrated with the conventional S/A to restore original binary instructions. The proposed techniques are applied to the fully-custom designed MCU with ARM Cortex-M0$^{TM}$ using 0.18um Magnachip Flash-embedded CMOS process and the benefits in terms of power consumption reduction are evaluated for Dhrystone$^{TM}$ benchmark. The profiling environment of instruction code executions is implemented by extending commercial ARM KEIL$^{TM}$ MDK (MCU Development Kit) with our custom-designed access analyzer.

• Journal of IKEEE
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• v.26 no.4
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• pp.537-544
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• 2022

This paper analyzes the occurrence and cause of bond wires fusing used in the manufacture of pulsed high power amplifiers. Recently GaN HEMT has been spotlight in the fields of electronic warfare, radar, base station and satellite communication. In order to produce the maximum output power, which is the main performance of the high-power amplifier, optimal impedance matching is required. And the material, diameter and number of bond wires must be determined in consideration of not only the rated current but also the heat generated by the transient current. In particular, it was confirmed that compound semiconductor with a wide energy band gap such as GaN trigger fusing of the bond wire due to an increase in thermal resistance when the design efficiency is low or the heat dissipation is insufficient. This data has been simulated for exothermic conditions, and it is expected to be used as a reference for applications using GaN devices as verified through IR microscope.

• Journal of Biomedical Engineering Research
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• v.32 no.1
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• pp.45-54
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• 2011

Cuff electrodes have a benefit for chronic electroneurogram(ENG) recording while minimizing nerve damage. However, the ENG signals are usually contaminated by electromyogram(EMG) activity from the surrounding muscle, the thermal noise generated within the source resistance, and the electric noise generated primarily at the first stage of the amplifier. This paper proposes a new cuff electrode to reduce the interference of EMG signals. An additional middle electrode was placed at the center of cuff electrode. As a result, the proposed cuff electrode achieved a higher signal-to-interference ratio compared to the conventional tripolar cuff. The cuff electrode was then assembled together with closure, headstage, and hermetic case including electronic circuits. This paper also presents a lownoise amplifier system to improve signal-to-noise ratio. The circuit was designed based on the noise analysis to minimize the electronic noise. The result shows that the total noise of the amplifier was below $1{\mu}V_{rms}$ for a cuff impedance of $1\;k{\Omega}$ and the common-mode rejection ratio was 115 dB at 1 kHz. In the current study, the performance of nerve cuff electrode system was evaluated by monitoring afferent nerve signals under mechanical stimuli in a rat animal model.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.1932-1938
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• 1999

In this paper, planar duplexer module combined with power amplifier is described. This new scheme is to enhance power efficiency as well as to minimize the size of RF circuit in CDMA phone. Each filter which was a part of duplexer, was realized with planar type and rearranged into the power amplifier module on the multilayer board. Each electrical specifications of existing power amplifier and duplexer were satisfied. Especially, ACPR performances measured at output power of 24dBm which is 2dB lower than that of a conventional one, meet IS-95 for a power amplifier of CDMA phone. Overall current about 80mA has been successfully saved as a result of new scheme. In addition, the module size has been reduced to be as small as 1.08CC.

• Journal of Broadcast Engineering
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• v.18 no.6
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• pp.884-894
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• 2013

In this paper, we investigate the characteristics of power amplifiers and simplified memoryless non-linear power amplifier models for energy efficient communication system. First, we present the transfer function of GaAs FET (Gallium Arsenide Field Effect Transistor) that is widely used for high power amplifier. From those investigations, we introduce the instantaneous efficiencies and methods of amplification by assuming that the saturated current is constant, while perfect linearity is exploited under knee voltage. Then, we discuss four non-linear power amplifier models in a baseband signal processing. Finally, we explain the specified total power consumption model in a base station to achieve the resonable analysis for energy efficient communication.

• BioChip Journal
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• v.12 no.4
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• pp.332-339
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• 2018

The future neuro-prosthetic devices would be required spikes data monitoring through sub-nanoscale transistors that enables to neuroscientists and clinicals for scalable, wireless and implantable applications. This research investigates the spikes monitoring through integrated CNT front-end amplifier for neuro-prosthetic diagnosis. The proposed carbon nanotube-based architecture consists of front-end amplifier (FEA), integrate fire neuron and pseudo resistor technique that observed high electrical performance through neural activity. A pseudo resistor technique ensures large input impedance for integrated FEA by compensating the input leakage current. While carbon nanotube based FEA provides low-voltage operation with directly impacts on the power consumption and also give detector size that demonstrates fidelity of the neural signals. The observed neural activity shows amplitude of spiking in terms of action potential up to $80{\mu}V$ while local field potentials up to 40 mV by using proposed architecture. This fully integrated architecture is implemented in Analog cadence virtuoso using design kit of CNT process. The fabricated chip consumes less power consumption of $2{\mu}W$ under the supply voltage of 0.7 V. The experimental and simulated results of the integrated FEA achieves $60G{\Omega}$ of input impedance and input referred noise of $8.5nv/{\sqrt{Hz}}$ over the wide bandwidth. Moreover, measured gain of the amplifier achieves 75 dB midband from range of 1 KHz to 35 KHz. The proposed research provides refreshing neural recording data through nanotube integrated circuit and which could be beneficial for the next generation neuroscientists.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.9
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• pp.1-9
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• 1997

Novel class A CMOS second-generation current conveyors (CCII) using 0.6.mu.m n-well standard CMOS process for high-frequency current-mode signal processing were developed. The CCII consists of a regulated current-cell for the voltage input and a cascode current mirror for the current output. In this architecture, the two input stages are coupled by current mirrors to reduce the current input impedance. Measurements of the fabricated cCII show that the current input impedance is 308 .ohm. and the 3-dB cutoff frequency when used as a voltage amplifier extends beyond 10MHz. The linear dynamic ranges of voltage and current are from -0.5V to 1.5V and from -100.mu.A to +120.mu.A for supply voltage V$\_$DD/ = -V$\_$SS/=2.5V, respectively. The power dissipation is 2 mW and the active chip area is 0.2 * 0.2 [mm$\^$2/].

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.79-85
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• 2009

The design of a 3.2 Gb/s serial link receiver in $0.18{\mu}m$ CMOS process is presented. The major factors limiting the performance of high-speed links are transmission channel bandwidth, timing uncertainty. The design uses a multi-level signaling(4-PAM) to overcome these problems. Moreover, to increase data bit-rate and lower BER, we designed this circuit by using a current mode amplifier, Current-mode Logic(CML) sampling latches. The 4-PAM receiver achieves 3.2 Gb/s and BER is less than $1.0\;{\times}\;10^{-12}$. The $0.5\;{\times}\;0.6\;mm^2$ chip consumes 49 mA at 3.2 Gb/s from a 1.8-V supply.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.10
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• pp.19-26
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• 1997

Novel class AB CMOS second-generation current conveyors (CCII) using 0.6.mu.m n-well CMOS process for high-frequency current-mode signal processing were developed. The CCII for low power operation consists of a class AB push-pull stage for the current input, a complementary source follower for the voltage input, and a cascode current mirror for the current output. In this architecture, the two input stages are coupled by current mirrors to reduce the current input impedance. Measurements of the fabricated CCII show that the current input impedance is 875.ohm. and the bandwidth of flat gain when used as a voltage amplifier extends beyond 4MHz. The power dissipation is 1.25mW and the active chip area is 0.2*0.15[mm$\^$2/].