• Journal of the Semiconductor & Display Technology
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• v.13 no.4
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• pp.65-70
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• 2014

This paper is to improve the problem of the LED dimming control system using the conventional PWM and DAC method. The conventional PWM method controls the average current to switch dimming signal. This method generates the flicker when controlling at a low current. In order to solve the problem, this system prevents the flicker with the DAC method. The LED is lit at micro-current flowing in the LED. And offset voltage is generated in the output of the DAC when the DAC output is very low voltage as 0V. This was resolved by the voltage drop of the output voltage to construct a negative offset circuit. In addition, the LED current can't flow as set values because of overheating of FET. In order to solve the problem, the 16 bits ADC in the microprocessor is a more accurate current control receives the LED current in comparison with the set value. Therefore, the LED dimming control system proposed in this paper showed the accurate and reliable more than conventional systems.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.39-45
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• 2011

This paper proposes a low power current-steering 10-bit DAC selecting clock enable signal. The proposed DAC reduces the clock power by cutting the clock signal to the current-source cells in wihich the data will not be changed. The proposed DAC was implemented using a 0.13${\mu}m$ CMOS process with $V_{DD}=1.2V$. Its core area is 0.21$mm^2$. It consumes 4.46mW at 1MHz signal frequency and 200MHz sampling rate. The clock power is reduced to 30.9% and 36.2% of a conventional DAC at 1.25MHz and 10MHz signal frequencies, respectively. The measured SFDRs are 72.8dB and 56.1dB at 1MHz and 50MHz signal frequencies, respectively.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.619-620
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• 2006

This paper presents a design of a 6-bit 2.704Gsamples/s D/A converter (DAC) for DS-CDMA UWB transceivers. The proposed DAC was designed with a current steering segmented 4+2 architecture for high frequency sampling rate. For low glitches, optimized deglitch circuit is adopted for the selection of current sources. The measured integral nonlinearity (INL) is -0.081 LSB and the measured differential nonlinearity (DNL) is -0.065 LSB. The DAC implemented in a 0.13um CMOS technology shows s spurious free dynamic range (SFDR) of 50dB from dc to Nyquist frequency. The prototype DAC consumes 28mW for a Nyquist sinusoidal output signal at a 2.704Gsamples/s. The chip has an active area of $0.76mm^2$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.4
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• pp.211-216
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• 2003

This work describes a 3 V 12b 100 MS/s CMOS digital-to-analog converter (DAC) for high-speed communication system applications. The proposed DAC is composed of a unit current-cell matrix for 8 MSBs and a binary-weighted array for 4 LSBs, trading-off linearity, power consumption, chip area, and glitch energy with this process. The low-glitch switch driving circuits are employed to improve linearity and dynamic performance. Current sources of the DAC are laid out separately from the current-cell switch matrix core block to reduce transient noise coupling. The prototype DAC is implemented in a 0.35 um n-well single-poly quad-metal CMOS technology and the measured DNL and INL are within ${\pm}0.75$ LSB and ${\pm}1.73$ LSB at 12b, respectively. The spurious-free dynamic range (SFDR) is 64 dB at 100 MS/s with a 10 MHz input sinewave. The DAC dissipates 91 mW at 3 V and occupies the active die area of $2.2{\;}mm{\;}{\times}{\;}2.0{\;}mm$

• 전자공학회논문지 IE
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• v.43 no.3
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• pp.6-12
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• 2006

This paper described an 8bit, 100Msample/s CMOS D/A converter using a glitch-time minimization technique for the high-speed sampling rate of 100MHz level. The proposed DAC was implemented in $0.35{\mu}m$ Hynix CMOS technology and adopts a current mode architecture to optimize sampling rate, resolution, chip area. The DAC linear characteristics was similar to the proposed specification and the prototype error between DNL and INL is less than $\pm$0.09LSB respectively. Also, the manufactured DAC chip was analyzed the cause of error operation and proposed the field considerations for chip test.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.1241-1246
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• 2005

This paper described an 8bit, 100Msample/s CMOS D/A converter using a glich-time minimization technique for the high-speed sampling rate of 100MHz level. The proposed DAC was implemented in 0,35um Hynix CMOS technology and adopts a current mode architecture to optimize sampling rate, resolution, chip area. The DAC linear characteristics was similar to the proposed specification the prototype error between DNL and INL is less than ${\pm}0.09LSB$ respectively. Also, fab-out chip was tested, analysed the cause of error operation, and proposed the field considerations for chip test.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.413-416
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• 1998

This paper presents a dAC calibration technique for high resolution and monolithic operation. The calibration technique consists of basic source, current memory cell (C.M) and current substrator. Current memory supplies the error current to basic source. Current substrator extracts the error current from the main source. It is simple and needs no special calibration period. The proposed current cell has high calibration performance and guarantees 100MHz operation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.658-665
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• 2014

The neural stimulators have been employed to the visual prostheses system based on the functional electrical stimulation (FES). Due to the size limitation of the implantable device, the smaller area of the unit current driver pixel is highly desired for higher resolution current stimulation system. This paper presents a 16-channel compact current-mode neural stimulator IC with digital to analog converter (DAC) sharing scheme for artificial retinal prostheses. The individual pixel circuits in the stimulator IC share a single 6 bit DAC using the sample-and-hold scheme. The DAC sharing scheme enables the simultaneous stimulation on multiple active pixels with a single DAC while maintaining small size and low power. The layout size of the stimulator circuit with the DAC sharing scheme is reduced to be 51.98 %, compared to the conventional scheme. The stimulator IC is designed using standard $0.18{\mu}m$ 1P6M process. The chip size except the I/O cells is $437{\mu}m{\times}501{\mu}m$.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.6
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• pp.28-36
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• 1997

In this work, a highly linear video-speed CMOS current-mode digital-to-analog converter (DAC) is proposed. A newswitching scheme for the current cell matrix of the DAC simultaneously reduces graded and symmetrical errors to improve integral nonlinearities (INL). The proposed DAC is designed to operate at any supply voltage between 3V and 5V, and minimizes the glitch energy of analog outputs with degliching circuits developed in this work. The prototype dAC was implemented in a LG 0.8um n-well single-poly double-metal CMOS technology. Experimental results show that the differential and integral nonlinearities are less than .+-. LSB and .+-.0.8LSB respectively. The DAC dissipates 75mW at a 3V single power supply and occupies a chip area of 2.4 mm * 2.9mm.

• Journal of rehabilitation welfare engineering & assistive technology
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• v.7 no.2
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• pp.13-18
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• 2013

In this paper design a 8 bit Current Steering D/A Converter for stimulating neuron signal. Proposed circuit in paper shows the conversion rate of 10KS/s and the power supply of 3.3V with 0.35um Magna chip CMOS process using full custom layout design. It employes segmented structure which consists of 3bit thermometer decoders and 5bit binary decoder for decreasing glitch noise and increasing resolution. So glitch energy is down by $10nV{\bullet}sec$ rather than binary weighted type DAC. And it makes use of low power current stimulator because of low LSB current. And it can make biphasic signal by connecting with Micro Controller Unit which controls period and amplitude of signal. As result of measurement INL is +0.56/-0.38 LSB and DNL is +0.3/-0.4 LSB. It shows great linearity. Power dissipation is 6mW.