• Journal of information and communication convergence engineering
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• v.18 no.4
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• pp.222-229
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• 2020

Recent multi-core processors for smart devices use per-core dynamic voltage and frequency scaling (DVFS) that enables independent voltage and frequency control of cores. However, because the conventional task scheduler was originally designed for per-core DVFS disabled processors, it cannot effectively utilize the per-core DVFS and simply allocates tasks evenly across all cores to core utilization with the same CPU frequency. Hence, we propose a novel task scheduler to effectively utilize percore DVFS, which enables each core to have the appropriate frequency, thereby improving performance and decreasing energy consumption. The proposed scheduler classifies applications into two types, based on performance-sensitivity and allows a performance-sensitive application to have a dedicated core, which maximizes core utilization. The experimental evaluations with a real off-the-shelf smart device showed that the proposed task scheduler reduced 13.6% of CPU energy (up to 28.3%) and 3.4% of execution time (up to 24.5%) on average, as compared to the conventional task scheduler.

• Journal of Korean Clinical Nursing Research
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• v.23 no.2
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• pp.189-201
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• 2017

Purpose: The aim of this study was to develop the nursing management core task and competency matrix for hospital unit managers. The perceived level of importance and performance of identified core competencies by unit managers were also investigated. Methods: Literature review and expert survey identified nursing management core task and competencies. Subsequently, the core task and competency matrix was developed and validated by expert panel. A survey of 196 nurse managers from 3 cities identified perceived importance and performance of core competiences. Results: Thirty-eight nursing management core task and thirty-seven nursing management core competencies were identified comprising five categories; Clinical practice knowledge, Evidence-based practice, Employee development, Strategic planning and Initiative. Based on the core task and competencies, the task and competency matrix for unit managers was developed. In the analysis of importance and performance of core competencies, the mean score of importance ($3.50{\pm}0.30$) was higher than the mean score of performance ($3.03{\pm}0.34$). Conclusion: The development of core task and competencies for unit managers in hospitals provides a guide for the development and evaluation of programs designed to increase competence of unit managers.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.11
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• pp.5465-5480
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• 2018

Energy-efficient task scheduling on multi-core server is a fundamental issue in green cloud computing. Multi-core processors are widely used in mobile devices, personal computers, and servers. Existing energy efficient task scheduling methods chiefly focus on reducing the energy consumption of the processor itself, and assume that the cores of the processor are controlled independently. However, the cores of some processors in the market are divided into several voltage islands, in each of which the cores must operate on the same status, and the cost of the server includes not only energy cost of the processor but also the energy of other components of the server and the cost of user waiting time. In this paper, we propose a cost-aware scheduling algorithm ICAS for computation intensive tasks on multi-core server. Tasks are first allocated to cores, and optimal frequency of each core is computed, and the frequency of each voltage island is finally determined. The experiments' results show the cost of ICAS is much lower than the existing method.

• Journal of the Korea Society of Computer and Information
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• v.16 no.6
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• pp.11-20
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• 2011

In this paper, we propose an optimal scheduling scheme that minimizes the energy consumption of a real-time video task on the multi-core platform supporting dynamic voltage and frequency scaling. Exploiting parallel execution on multiple cores for less energy consumption, the propose scheme allocates an appropriate number of cores to the task execution, turns off the power of unused cores, and assigns the lowest clock frequency meeting the deadline. Our experiments show that the proposed scheme saves a significant amount of energy, up to 67% and 89% of energy consumed by two previous methods that execute the task on a single core and on all cores respectively.

• Transactions of the Korean Society of Automotive Engineers
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• v.24 no.2
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• pp.127-136
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• 2016

The camera based object detection systems should satisfy the recognition performance as well as real-time constraints. Particularly, in safety-critical systems such as Autonomous Emergency Braking (AEB), the real-time constraints significantly affects the system performance. Recently, multi-core processors and system-on-chip technologies are widely used to accelerate the object detection algorithm by distributing computational loads. However, due to the advanced hardware, the complexity of system architecture is increased even though additional hardwares improve the real-time performance. The increased complexity also cause difficulty in migration of existing algorithms and development of new algorithms. In this paper, to improve real-time performance and design complexity, a task scheduling strategy is proposed for visual object tracking systems. The real-time performance of the vision algorithm is increased by applying pipelining to task scheduling in a multi-core processor. Finally, the proposed task scheduling algorithm is applied to crosswalk detection and tracking system to prove the effectiveness of the proposed strategy.

• The Journal of the Korea Contents Association
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• v.11 no.5
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• pp.328-337
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• 2011

For certify job characteristic affecting attitude of employee, this study is to examine the relationship between core job characteristics(skill variety, task identity, task significance, autonomy, feedback) and attitude(job satisfaction, organizational commitment, turnover intention) of small business from a 'human resource management' point of view. Concretely, it is confirmed whether how influence of ore job characteristics on attitude and whether there is a moderating effect of growth needs of strength between core job characteristics and attitude of small business. The results of regression analysis using 315 domestic employees are as followings. First, it is confirmed that the skill variety and task significance has influence on job satisfaction positively, skill variety and feedback has influence on organizational commitment positively, and skill variety and feedback has influence on turnover intention negatively. Second, there is moderating effect only the relationship between task significance and turnover intention. On the basis of these study results, it suggested strategic implications to job design and business strategy for heightening attitude of small business employees.

• ETRI Journal
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• v.37 no.1
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• pp.118-127
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• 2015

The power consumption of 3D many-core processors can be reduced, and the power delivery of such processors can be improved by introducing voltage island (VI) design using on-chip voltage regulators. With the dramatic growth in the number of cores that are integrated in a processor, however, it is infeasible to adopt per-core VI design. We propose a 3D many-core processor architecture that consists of multiple voltage clusters, where each has a set of cores that share an on-chip voltage regulator. Based on the architecture, the steady state temperature is analyzed so that the thermal characteristic of each voltage cluster is known. In the voltage scaling and task scheduling stages, the thermal characteristics and communication between cores is considered. The consideration of the thermal characteristics enables the proposed VI formation to reduce the total energy consumption, peak temperature, and temperature gradients in 3D many-core processors.

• Journal of Korea Society of Industrial Information Systems
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• v.26 no.5
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• pp.11-19
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• 2021

In this paper, we proposed an asymmetric multi-core processor scheduling scheme which is based on the mileage of each core. We considered a big-LITTLE multi-core processor structure, which consists of low power consuming LITTLE cores with general performance and high power consuming big cores with high performance. If a task needs to be processed, the processor decides a core type (big or LITTLE) to handle the task, and then investigate the core with the shortest mileage among unoccupied cores. Then assigns the task to the core. We developed a mileage-based balancing algorithm for asymmetric multi-core assignment and showed that the proposed scheduling scheme is more cost-effective compared to the traditional scheme from a management perspective. Simulation is also conducted for the purpose of performance evaluation of our proposed algorithm.

• Journal of Fisheries and Marine Sciences Education
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• v.23 no.3
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• pp.433-444
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• 2011

The purpose of this study is to examine the task of the policy on the collecting cargoes of the Japanese container ports. Although the ports of Asia countries such as China, South Korea have increased the amount of cargoes dramatically since the latter half of 1990s, the amount of cargoes Japanese container ports deal with have increased within narrow limits. As a result of this trend, the position of Japanese ports as hub-ports has been falling down. The times of main liners linked with North America and Europe stopping at Japanese ports have continued to decrease. So Japan container ports need the policy to increase the amount of cargoes in order to avoid becoming feeder ports. This policy is to collect domestic cargoes which are transshipped in Asia ports such as Busan port from Japanese regional ports to core ports. By collecting domestic cargoes to Japanese core ports intensively, the times of international main liners stopping at Japanese core ports will increase. It's important to support the domestic liners linking between Japanese regional ports and core ports in order to collecting domestic cargoes to Japanese core ports effectively. In addition the role of Japanese government to achieve the coordination between Japanese regional ports and core ports is indispensable.

• Journal of Information Processing Systems
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• v.8 no.2
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• pp.331-346
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• 2012

Task-based programming is becoming the state-of-the-art method of choice for extracting the desired performance from multi-core chips. It expresses a program in terms of lightweight logical tasks rather than heavyweight threads. Intel Threading Building Blocks (TBB) is a task-based parallel programming paradigm for multi-core processors. The performance gain of this paradigm depends to a great extent on the efficiency of its parallel constructs. The parallel overheads incurred by parallel constructs determine the ability for creating large-scale parallel programs, especially in the case of fine-grain parallelism. This paper presents a study of TBB parallelization overheads. For this purpose, a TBB micro-benchmarks suite called TBBench has been developed. We use TBBench to evaluate the parallelization overheads of TBB on different multi-core machines and different compilers. We report in detail in this paper on the relative overheads and analyze the running results.