• Journal of Power Electronics
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• v.18 no.5
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• pp.1523-1535
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• 2018

High-performance Phase-Locked Loops (PLLs) are critical for grid synchronization in grid-tied power electronic applications. In this paper, a new single-phase All Digital Phase-Locked Loop (ADPLL) is proposed. It features fast transient response and good robustness under distorted grid conditions. It is designed for Field Programmable Gate Array (FPGA) implementation. As a result, a high sampling frequency of 1MHz can be obtained. In addition, a new OSG is adopted to track the power frequency, improve the harmonic rejection and remove the dc offset. Unlike previous methods, it avoids extra feedback loop, which results in an enlarged system bandwidth, enhanced stability and improved dynamic performance. In this case, a new parameter optimization method with consideration of loop delay is employed to achieve a fast dynamic response and guarantee accuracy. The Phase Detector (PD) and Voltage Controlled Oscillator (VCO) are realized by a Coordinate Rotation Digital Computer (CORDIC) algorithm and a Direct Digital Synthesis (DDS) block, respectively. The whole PLL system is finally produced on a FPGA. A theoretical analysis and experiments under various distorted grid conditions, including voltage sag, phase jump, frequency step, harmonics distortion, dc offset and combined disturbances, are also presented to verify the fast dynamic response and good robustness of the ADPLL.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.14 no.3
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• pp.1337-1362
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• 2020

Advances in localization-based technologies and the increase in ubiquitous computing have led to a growing interest in location-based applications and services. High accuracy of the position of a wireless device is still a crucial requirement to be satisfied. Firstly, the rapid development of wireless communication technologies has affected the location accuracy of radio monitoring systems employed locally and globally. Secondly, the location is determined using standard complex computing methods and needs a relatively long execution time. In this paper, two geolocalization techniques, based on trigonometric and CORDIC computing processes, are proposed and implemented for Bluetooth-based indoor monitoring applications. Theoretical analysis and simulation results are investigated in terms of accuracy, scalability, and responsiveness. They show that the proposed techniques can locate a target wireless device accurately and are well suited for timing estimation.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.49 no.3
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• pp.31-37
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• 2012

This paper presents an efficient hardware architecture to enable the high-speed Givens rotation-based QR decomposition. The proposed architecture achieves a highly parallel givens rotation process by maximizing the number of pivots selected for parallel zero-insertions. Sign-select lookahed (SSL)-CORDIC is also efficiently used for the high-speed givens rotation. The performance of QR decomposition hardware considerably increases compared to the conventional triangular systolic array (TSA) architecture. Moreover, the circuit area of QR decomposition hardware was reduced by decreasing the number of flip-flops for holding the pre-computed results during the decomposition process. The proposed QR decomposition hardware was implemented using TSMC $0.25{\mu}m$ technology. The experimental results show that the proposed architecture achieves up to 70 % speed-up over the TACR/TSA-based architecture for the $8{\times}8$ matrix decomposition.

• Journal of the Korea Society of Computer and Information
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• v.17 no.12
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• pp.49-60
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• 2012

In this paper, we propose a hardware design for correction of barrel distortion using the nearest coordinates in the corrected image. Because it applies the nearest distance on corrected image rather than adjacent distance on distorted image, the picture quality is improved by the image whole area, solve the staircase phenomenon in the exterior area. But, because of additional arithmetic operation using design of bilinear interpolation, required arithmetic operation is increased. Look up table(LUT) structure is proposed in order to solve this, coordinate rotation digital computer(CORDIC) algorithm is applied. The results of the synthesis using Design compiler, the design of implementing all processes of the interpolation method with the hardware is higher than the previous design about the throughput, In case of the rear camera, the design of using LUT and hardware together can reduce the size than the design of implementing all processes with the hardware.

• Journal of Information Processing Systems
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• v.18 no.3
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• pp.293-301
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• 2022

Direction of arrival (DOA) estimation of space signals is a basic problem in array signal processing. DOA estimation based on the multiple signal classification (MUSIC) algorithm can theoretically overcome the Rayleigh limit and achieve super resolution. However, owing to its inadequate real-time performance and accuracy in practical engineering applications, its applications are limited. To address this problem, in this study, a DOA estimation algorithm with high parallelism and precision based on an analysis of the characteristics of complex matrix eigenvalue decomposition and the coordinate rotation digital computer (CORDIC) algorithm is proposed. For parallel and single precision, floating-point numbers are used to construct an orthogonal identity matrix. Thus, the efficiency and accuracy of the algorithm are guaranteed. Furthermore, the accuracy and computation of the fixed-point algorithm, double-precision floating-point algorithm, and proposed algorithm are compared. Without increasing complexity, the proposed algorithm can achieve remarkably higher accuracy and efficiency than the fixed-point algorithm and double-precision floating-point calculations, respectively.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.3
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• pp.340-344
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• 1986

This paper shows that we can design a vector-coordinate rotation processor and obtain the approximate evaluations of sine and cosine based upon the use of residue number systems. The algorithm results in the considerable improvement of the computation speed when compared to CORDIC algorithm. The results from computer simulation show that the mean error of sine and cosine is 0.0025 and the mean error of coordinate rotation arithmatic is 0.65. Also, the proposed processor has the efficiency for the design and fabrication of integrated circuit, because it consists of the array of idecntially structured look-up tables.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.3
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• pp.345-350
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• 1986

This paper deseribes the design of a vector-coordinate rotation processor and the apporoximate evaluations of sine and consine based upon the use of residue number systems. The proposed algorithm results in a considerable improvement of computational speed as compared to the CORDIC algorithm. According to the results of computer simulation, the mean error of sine and cosine is 0.0025, and the mean error of coorcinate rotation arithmatic is 0.65. The proposed processor has the efficiency for the design and fabrication of integrated circuits, because it consists of an array of identical lookup tables.

• The Journal of Information Technology
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• v.8 no.3
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• pp.1-10
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• 2005

Cosine and Sine function is widely used for the arithmetic, translation, object drawing, Simulation and etc. of Computer Graphics in Natural Science and Engineering. In general, Cordic Algorithm is effective method since it has relatively small size and simple architecture on trigonometric function generation. However profitably it has those merits, the problem of operation speed is occurred. In graphic display system, the operation result of object drawing is quantized and has the condition that is satisfied with rms error less than 1. So in this paper, the proposed generator is composed of partition operation at each ${\pi}/4$ and basic Cosine, Sine function generator in the range of $0{\sim}{\pi}/4$ using the lower order of Tayler's series in an acceptable error range, that enlarge the range of $0{\sim}2{\pi}$ according to a definition of the trigonometric function for the purpose of having a high speed Cosine, Sine function generation. And, division operator using code partition for divisor three is proposed, the proposed function generator has high speed operation, but it has the problems in the other application parts with accurate results, is need to increase the speed of the multiplication.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.9C
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• pp.729-734
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• 2010

In the initial stage of the communications between a base station and a satellite transponder, the base station transmits the frequency-sweeping un-modulated up-link carrier within a certain frequency range to acquire the doppler frequency shift and signal power between the base station and the satellite in orbital flight. The satellite transponder acquires and tracks the carrier in order to initialize the communication. To control such initialization process, the satellite receiver should analyze the input carrier signal in various ways. This paper presents an SNR estimation algorithm to control the initialization process. The proposed algorithm converts the input signal into the baseband polar coordinate representation and estimates the SNR via the statistics of the angular signal components as well as the status parameters to control the receiver. The Monte-Carlo simulations shows the validity of the estimation proposed.