• Journal of the Microelectronics and Packaging Society
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• v.13 no.3 s.40
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• pp.13-17
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• 2006

Dense and periodic arrays of holes and tungsten none dots were fabricated on silicon oxide and silicon. The holes were approximately 25 nm wide, 40 nm deep, and 60 nm apart. To obtain nano-size patterns, self-assembling resists were used to produce layer of hexagonally ordered parallel cylinders of polymethylmethacrylate(PMMA) in polystyrene(PS) matrix. The PMMA cylinders were degraded and removed with acetic acid rinse to produce a PS mask for pattern transfer. The silicon oxide was removed by fluorine-based reactive ion etching(RIE). Selectively deposited tungsten nano dots were formed inside nano-sized trench by using a low pressure chemical vapor deposition(LPCVD) method. Tungsten nano dot and trenched silicon sizes were 26 nm and 30 nm, respectively.

• Journal of the Korean Vacuum Society
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• v.16 no.5
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• pp.366-370
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• 2007

Nano-scopic holes which are distributed densely and uniformly were fabricated on $SiO_2$ surface. Self-assembling resists were used to produce a layer of uniformly distributed parallel poly methyl methacrylate (PMMA) cylinders in a polystyrene (PS) matrix. The PMMA cylinders were degraded and removed by acetic acid rinsing. Subsequently, PS nanotemplates were fabricated. The patterned holes of PS template were approximately $8{\sim}30\;nm$ wide, 40 nm deep, and 60 nm apart. The porous PS template was used as a dry etching mask to transfer the pattern of PS template into the silicon oxide thin film during reactive ion etching (RIE) process. The sizes of the patterned holes on $SiO_2$ layer were $9{\sim}33\;nm$. After pattern transfer by RIE, uniformly distributed holes of which size were in the range of $6{\sim}22\;nm$ were fabricated on Si substrate. Sizes of the patterned holes were controllable by PMMA molecular weight.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.17-20
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• 2000

We have enhanced the yield of 0.25 ${\mu}{\textrm}{m}$ T-gate $Al_{0.25}$G $a_{0.75}$As/I $n_{0.2}$G $a_{0.8}$As P-HEMT using three-layer E-beam lithography process and selective etching process. The three-layer resist structure (PMMA/copolymer/ PMMA=2000 $\AA$/3000 $\AA$/2000 $\AA$) and three developers (Benzene：IPA=1：1,Methanol：IPA =1：1,MIBK：IPA=1：3) were used for fabrication of a wide-head T-gate by the conventional double E-beam exposure technology. Also 1 wt% citric acid： $H_2O$$_2$：N $H_{4}$OH(200m1：4ml：2.2ml) solution were used for uniform gate recess. The etching selectivity of GaAs over $Al_{0.25}$G $a_{0.75}$As is measured to be 80. So these P-HEMT processes can be used in X-band MMIC LNA fabrication.ion.ion.ion.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.2 s.43
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• pp.17-21
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• 2007

Dense and periodic arrays of holes and Si nano dots were fabricated on silicon substrate. The nanopatterned holes were approximately $15{\sim}40nm$ wide, 40 nm deep and $40{\sim}80\;nm$ apart. To obtain nano-size patterns, self?assembling diblock copolymer were used to produce layer of hexagonaly ordered parallel cylinders of polymethylmethacrylate (PMMA) in polystyrene(PS) matrix. The PMMA cylinders were degraded and removed with acetic acid rinse to produce a PS. $100\;{\AA}-thick$ Au thin film was deposited by using e-beam evaporator. PS template was removed by lift-off process. Arrays of Au nano dots were transferred by using Fluorine-based reactive ion etching(RE). Au nano dots were removed by sulfuric acid. Si nano dots size and height were $30{\sim}70\;nm$ and $10{\sim}20\;nm$ respectively.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.4
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• pp.29-32
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• 2009

Dense and periodic arrays of nano-sized holes were patterned in oxide thin film on GaAs substrate. To obtain the nano-size patterns, self-assembling diblock copolymer was used to produce thin film of uniformly distributed parallel cylinders of polymethylmethacrylate (PMMA) in polystyrene (PS) matrix. The PMMA cylinders were removed with UV expose and acetic acid rinse to produce PS nanotemplate. By reactive ion etching, pattern of the PS template was transferred to under laid silicon oxide layer. Transferred patterns were reached to the GaAs substrate by controlling the dry etching time. We confirmed the achievement of etching through the removing oxide layer and observation of GaAs substrate surface. Optimized etching time was 90 to 100 sec. Pore sizes of the nanopattern in the silicon oxide layer were 20~22 nm.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.469-469
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• 2011

고효율 염료감응형 태양전지(DSSC, Dye-Sensitized Solar Cell)의 구현을 위해서 유용한 방법중 하나는 정렬된 기공 (pore)을 $TiO_2$막 내에 형성시키는 것이다. 메조포러스 (mesoporous) $TiO_2$막은 dip coating이나 spin coating과 같은 방법으로 주로 증착되고 있으며, P123이나 F127과 같은 amphiphilic triblock copolymer를 메조포러스 구조를 만들기 위한 뼈대로 사용하고 있다. 또한, 이렇게 생성된 구조에서 amphiphilic triblock copolymer는 열처리 공정을 통하여 쉽게 제거될 수 있다. 고효율 태양전지를 구현하는 또 다른 방법으로는 패턴 된 기판을 사용하는 것이다. 패턴 된 기판은 빛의 반사를 억제하여 흡수율을 높이는 역할을 한다. 그러나 패턴 된 기판 위에서 메조포러스 $TiO_2$막의 형성에 관한 연구는 부족한 실정이다. 본 연구에서는 spin coating 방법으로 패턴 된 Si (111) 기판 위에 메조포러스 $TiO_2$를 성장하고 그 미세구조를 분석하였다. 패턴 된 기판은 nanosphere lithography(NSL) 법으로 mask를 증착한 후 건식 식각 (dry etching) 공정을 통해서 제작되었으며, 마스크와 불순물 등 은 초음파 세척 등으로 제거되었다. 메조포러스 $TiO_2$막은 1-propanol, P123, titanium isopropoxide와 HCl을 섞어 만든 용액으로 1 cm${\times}$1 cm 기판 위에 3000 rpm과 4000 rpm으로 각각 증착하였으며, 5일 동안 4도에서 에이징한 후 350도에서 3시간 열처리하였다. 이렇게 형성한 메조포러스 막의 형상과 미세구조적 특성이 주사전자현미경(SEM, scanning electron microscope), X-선 회절(XRD, X-ray diffraction) 등을 이용하여 연구되었다. 특히, 증착 조건에 따른 메조포러스 $TiO_2$박막의 형성 기구에 관한 고찰이 진행되었다. 나아가, $TiO_2$박막과 패턴 사이에 형성되는 계면 구조에 관한 연구를 투과전자현미경을 이용하여 진행하였다.

• Journal of the Korean Vacuum Society
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• v.16 no.1
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• pp.65-73
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• 2007

The control of surface properties and spatial presentation of functional molecules within a microfluidic channel is important for the development of diagnostic assays, microreactors, and for performing fundamental studies of cell biology and fluid mechanics. Here, we present soft lithographic methods to create robust microchannels with patterned microstructures inside the channel. The patterned regions were protected from oxygen plasma by controlling the dimensions of the poly(dimethylsiloxane)(PDMS) mold as well as the sequence of fabrication steps. The approach was used to pattern a non-biofouling polyethylene glycol(PEG)-based copolymer or the polysaccharide hyaluronic acid(HA) within microfluidic channels. These non-biofouling patterns were then used to fabricate arrays of fibronectin(FN) and bovine serum albumin(BSA) as well as mammalian cells.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.05a
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• pp.24.2-24.2
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• 2009

Nanostuctures such as nanodot and nanowire have been extensively studied as building blocks for nanoscale devices. However, the direct growth of the nanostuctures at the desired position is one of the most important requirements for realization of the practical devices with high integrity. Self-assembled nanotemplate is one of viable methods to produce highly-ordered nanostructures because it exhibits the highly ordered nanometer-sized pattern without resorting to lithography techniques. And selective epitaxial growth (SEG) can be a proper method for nanostructure fabrication because selective growth on the patterned openings obtained from nanotemplate can be a proper direction to achieve high level of control and reproducibility of nanostructucture fabrication. Especially, SiGe has led to the development of semiconductor devices in which the band structure is varied by the composition and strain distribution, and nanostructures of SiGe has represented new class of devices such nanowire metal-oxide-semiconductor field-effect transistors and photovoltaics. So, in this study, various shaped SiGe nanostructures were selectively grown on Si substrate through ultrahigh vacuum chemical vapor deposition (UHV-CVD) of SiGe on the hexagonally arranged Si openings obtained using nanotemplates. We adopted two types of nanotemplates in this study; anodic aluminum oxide (AAO) and diblock copolymer of PS-b-PMMA. Well ordered and various shaped nanostructure of SiGe, nanodots and nanowire, were fabricated on Si openings by combining SEG of SiGe to self-assembled nanotemplates. Nanostructure fabrication method adopted in this study will open up the easy way to produce the integrated nanoelectronic device arrays using the well ordered nano-building blocks obtained from the combination of SEG and self-assembled nanotemplates.