• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 A
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• pp.267-270
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• 2003

This paper proposes high performance $8{\times}8$ multiplier using current-mode quaternary logic technique. The multiplier is functionally partitioned into the following major sections: partial product generator block(binary-quaternary logic conversion), current-mode quaternary logic full-adder block, quaternary-binary logic conversion block. The proposed multiplier has 4.5ns of propagation delay and 6.1mW of power consumption. Also, this multiplier can easily adapted to binary system by the encoder, the decoder. This circuit is simulated under 0.35um standard CMOS technology, 5uA unit current, and 3.3V supply voltage using Hspice.

• 항공우주시스템공학회지
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• 제9권1호
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• pp.12-18
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• 2015

The inter-conversion between different control laws in flight has a lot of risk. The SWM(Switching Mechanism) including logic and stand-by mode is designed to analyze the transient response of aircraft during inter-conversion between different control laws, based on the in-house software for non-real-time and real-time simulation. The SWM applies the fader logic of TFS(Transient Free Switch) to minimize the transient response of an aircraft during the inter-conversion, and applies the reset '0' type of the stand-by mode to prevent surface saturation due to integrator effect in the disengaged flight control law. The transition time is also important to minimize the objectionable transient response in the inter-conversion, as well as the transition control law design. This paper addresses the results of non-real-time simulation for the characteristics of transient response to different transition time to select the adequate transient time, and the real-time pilot evaluation, using SSWM(Software Switching Mechanism) and HSWM(Hardware Switching Mechanism), which is met for Level 1 flying qualities and assures safety of flight.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2011년도 추계학술대회
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• pp.285-286
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• 2011

Maximum Power Point Tracker (MPPT) is the big issue in generating power based on Wind Energy Conversion System. In case of unknown turbine characteristic, it is useful to implement MPPT based on fuzzy logic control. This kind of control is able to find the value of duty cycle to meet maximum power point at particular wind speed. There are many methods to develop MPPT based fuzzy logic controls. In this paper, two of the methods are compared both at low and high fluctuating wind speed.

• 제어로봇시스템학회논문지
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• 제7권12호
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• pp.1009-1014
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• 2001

The ladder diagram (LD) for programmable logic controllers (PLCs) ar responsible for much important roles in advance industrial automation. As automated systems become more complex the design procedures of the system become more difficult as well. Hence. the design automation issues based on discrete event models(DEMs) are receiving more attention. One of the popular ways of tackling these problems is employing Petri nets. In this paper, we use the modified automation Petri net(MAPN) to model the manufacturing system and the modified token passing logic (MTPL) method conversion (ECC) algorithm based on the MAPN and the MTPL Finally, an example of the manufacturing system is provided to illustrate the proposed ECC algorithm.

• 대한전기학회논문지:시스템및제어부문D
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• 제53권11호
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• pp.753-759
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• 2004

This paper presents a modeling and simulation of a fuzzy controller for maximum power extraction of a grid-connected wind energy conversion system with a link of a rectifier and an inverter. It discusses the maximum power control algorithm for a wind turbine and proposes, in a graphical form, the relationships of wind turbine output, rotor speed, power coefficient, tip-speed ratio with wind speed when the wind turbine is operated under the maximum power control. The control objective is to always extract maximum power from wind and transfer the power to the utility by controlling both the pitch angle of the wind turbine blades and the inverter firing angle. Pitch control method is mechanically complicated, but the control performance is better than that of the stall regulation method. The simulation results performed on MATLAB will show the variation of generator's rotor angle and rotor speed, pitch angle, and generator output.

• 한국광학회지
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• 제13권2호
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• pp.151-154
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• 2002

선광(all-optical) OR 논리소자가 반도체 광증폭기 (SOA)의 이득포화와 파장변환 특성을 이용하여 구현되었다. 전광(all-optical) OR 논리소자는 이득의 비선형성에 의해 동작되므로 SOA의 이득포화를 충분히 얻기 위해 펌프신호는 SOA의 입력단에서 어븀 첨가 광섬유 증복기(EDFA)에 의해 증폭되었다. 전광 OR논리소자의 동작특성은 2.5 Gbit/s에서 성공적으로 측정되었다.

• 전기전자학회논문지
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• 제9권1호
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• pp.1-6
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• 2005

본 논문에서는 CMOS 다치 논리회로를 이용한 고성능 곱셈기를 제안하였다. 이 곱셈기는 Modified Baugh-Wooley 곱셈 알고리즘과 전류모드 4치 논리회로를 적용하여 트랜지스터의 수를 감소시키고 이에 따른 상호연결 복잡도를 감소시켜 곱셈기 성능을 향상시켰다. 제안한 회로는 전압모드 2진 논리신호를 전류모드 4치 논리신호로 확장하는 동시에 부분 곱을 생성하고 4치 논리 가산기를 통해 가산을 수행 후 전류모드 4치-2진 논리 변환 디코더를 이용하여 출력을 생성한다. 이와 같이 곱셈기의 내부는 전류모드 4치 논리로 구성하였으며 입출력단은 전압모드 2진 논리회로의 입,출력을 사용함으로써 기존의 시스템과 완벽한 호환성을 갖도록 설계하였다. 이 곱셈기는 6.1mW의 소비전력과 4.5ns의 전달지연을 보였으며, 트랜지스터 수는 두 개의 비교 대상 회로에 비해 60%, 43% 노드 수는 46%, 35% 감소하였다. 설계한 회로는 3.3V의 공급전원과 단위전류 5uA를 사용하여, 0.35um 표준 CMOS 공정을 이용하여 구현하였으며, HSPICE를 사용하여 그 타당성을 입증하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.735-738
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• 1998

To develop an effective virtual prototyping methodology for the PLC(Programmable Logic Controller) based real-time systems, a conversion algorithm from RLL(Relay Ladder Logic) to statechart is presented in this paper. The RLL is the main programming language to represent the operation of the PLC, and the statechart is the most widely used tool in the field of virtual prototyping in order to represent the behaviour of real-time systems. A virtual prototyping for an example case is implemened to evaluate the benefit of the proposed algorithm.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 심포지엄 논문집 정보 및 제어부문
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• pp.148-151
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• 2005

This paper proposes a high speed interface using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit that serial binary data are received and converted into parallel redundant multi-valued data, and decoding circuit that convert redundant multi-valued data to parallel binary data. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, a 1:4 demultiplexer (DEMUX, serial-parallel converter) IC was designed using a 0.35${\mu}m$ standard CMOS Process. Proposed demultiplexer is achieved an operating speed of 3Gb/s with a supply voltage of 3.3V and with power consumption of 48mW. Designed circuit is limited by maximum operating frequency of process. Therefore, this circuit is to achieve CMOS communication ICs with an operating speed greater than 3Gb/s in submicron process of high of operating frequency.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.699-702
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• 2005

This paper describes a high speed interface using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit and decoding circuit. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, a 1:4 DEMUX (demultiplexer) was designed using a 0.35um standard CMOS technology. Proposed circuit is achieved an operating speed of 4.5Gb/s with a supply voltage of 3.3V and with power consumption of 53mW.