• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.6C
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• pp.355-360
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• 2011

In this paper, we propose a new context-based adaptive binary arithmetic coding (CABAC) method for lossless image compression. Since the conventional CABAC in H.264/AVC was originally designed for lossy coding, it does not yield adequate performance during lossless coding. Therefore, we proposed an improved CABAC method for lossless intra coding by considering the statistical characteristics of residual data in lossless intra coding. Experimental results showed that the proposed method reduced the bit rate by 18.2%, compared to the conventional CABAC for lossless intra coding.

• Journal of IKEEE
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• v.21 no.3
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• pp.280-283
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• 2017

HEVC (high efficiency video coding) exploits CABAC (context-based adaptive binary arithmetic coding) for entropy coding, where a context model estimates the probability for each syntax element. In this paper, a context modeler was designed and implemented for CABAC decoding. lookup table was used to reduce computation and to increase speed. 12 simulations for HEVC standard test sequences and encoder configurations were performed, and the context modeler was verified to perform correction operations. The designed context modeler was synthesized in 0.18um technology. Maximum frequency, maximum throughput, and gate count are 200 MHz, 200 Mbin/s, and 29,268 gates, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.42-49
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• 2007

CABAC(Context-based Adaptive Binary Arithmetic Coding) among various entropy coding schemes which are used to improve compression efficiency in H.264/AVC has a high hardware complexity and the fast calculation is difficult because data dependancy exists in the bit-serial process. In this paper, the proposed architecture efficiently compose the renormalization process of binary arithmetic encoder which is an important part of CABAC used in H.264/AVC. At every clock cycle, the input symbol is encoded regardless of the iteration of the renormalization process for every input symbol. Also, the proposed architecture can deal with the bitsOutstanding up to 127 which is adopted to handle the carry generation problem and encode input symbol without stall. The proposed architecture with three-stage pipeline has been synthesized using the 0.18um Dongbu-Anam standard cell library and can be operated at 290MHz.

• Journal of IKEEE
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• v.18 no.4
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• pp.630-635
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• 2014

In this paper, hardware architecture of BAE (binary arithmetic encoder) was proposed for HEVC (high efficiency video coding) CABAC (context-based adaptive binary arithmetic coding) encoder. It can encode each bin in a single cycle. It consists of controller, regular encoding engine, bypass encoding engine, and termination engine. The proposed BAE was designed in Verilog HDL, and it was implemented in 180 nm technology. Its operating speed, gate count, and power consumption are 180 MHz, 3,690 gates, and 2.88 mW, respectively.

• Journal of Advanced Navigation Technology
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• v.18 no.6
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• pp.600-608
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• 2014

In this paper, CABAC H/W module is developed using co-design method. After entire H.264/AVC encoder was developed with C using reference SW(JM), CABAC H/W IP is developed as a block in H.264/AVC encoder. Context modeller of CABAC is included on the hardware to update the changed value during binary encoding, which enables the efficient usage of memory and the efficient design of I/O stream. Hardware IP is co-operated with the reference software JM of H.264/AVC, and executed on Virtex-4 FX60 FPGA on ML410 board. Functional simulation is done using Modelsim. Compared with existing H/W module of CABAC with register-level design, the development time is reduced greatly and software engineer can design H/W module more easily. As a result, the used amount of slice in CABAC is less than 1/3 of that of CAVLC module. The proposed co-design method is useful to provide hardware accelerator in need of speed-up of high efficient video encoder in embedded system.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.425-428
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• 2005

This paper is made up Advanced Image Coding(AIC) that combines algorithms from next generation image coding standard, H.264/MPEG-4 Part 10 advanced video coding(AVC) and still image compression standard, JPEG(Joint Photographic Experts Group). AIC combines intra frame block prediction from H.264 with a JPEG style discrete cosine transform and quantization, followed by Context-based Adaptive Binary Arithmetic Coding(CABAC) as used in H.264. In this paper, we analyzes the efficiency of the AIC algorithm and JPEG and JPEG-2000, and it presents of result.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.687-690
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• 2005

H.264/AVC에서 압축 효율을 향상시키기 위해 사용된 entropy coding중에 CABAC(Context-based Adaptive Binary Arithmetic Coding)은 하드웨어 복잡도가 높고 bit-serial 과정에서 data dependancy가 존재하기 때문에 빠른 연산이 어렵다. 본 논문에서는 adaptive arithmetic encoder와 정규화 과정을 효율적으로 구성하여 각 입력 심벌이 정규화 과정의 반복횟수에 관계없이 고정된 cycle에 encoding이 되도록 하였다. 제안한 구조는 pipeline으로 구성하기 용이하며, 이 경우 매 cycle에 한 입력 심벌의 encoding이 가능하다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.61-68
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• 2008

In this paper, we propose an efficient hardware architecture and algorithm to increase an encoding process rate and implement a hardware for CABAC (Context Adaptive Binary Arithmetic Coding) which is used with one of the entropy coding ways for the latest video compression technique, H.264/AVC (Advanced Video Coding). CABAC typically provides a better high compression performance maximum 15% compared with CAVLC. However, the complexity of operation of CABAC is significantly higher than the CAVLC. Because of complicated data dependency during the encoding process, the complexity of operation is higher. Therefore, various architectures were proposed to reduce an amount of operation. However, they have still latency on account of complicated data dependency. The proposed architecture has two techniques to implement efficient pipeline architecture. The one is quick calculation of 7, 8th bits used to calculate a probability is the first step in Binary arithmetic coding. The other is one step reduced pipeline arcbitecture when the type of the encoded symbols is MPS. By adopting these two techniques, the required processing time was reduced about 27-29% compared with previous architectures. It is designed in a hardware description language and total logic gate count is 19K using 0.18um standard cell library.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2013.06a
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• pp.278-279
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• 2013

최근에 완료된 HEVC(High Efficiency Video Coding) 비디오 압축 표준은 H.264/AVC에 비해 2배 이상 향상된 압축 효율을 제공한다. 현재 진행 중인 HEVC 확장 (extension) 작업에서는 손실 및 무손실 부호화에서 4:2:2 및 4:4:4 색차 포맷과 최대 12비트 깊이를 지원하는 고급 프로파일을 개발하고 있다. 현재까지 개발된 HEVC의 CABAC(Context-based Adaptive Binary Arithmetic Coding)은 손실 부호화 환경에 적합하게 설계되었기 때문에 무손실 부호화 환경에서 최적의 부호화 성능을 제공하지 못한다. 본 논문에서는 4:4:4 색차 포맷 영상의 무손실 화면내 부호화 환경에서 잔여 신호의 통계적 특성을 고려한 향상된 CABAC 잔여 데이터 부호화 방법을 제안한다. 실험 결과를 통해, 본 논문에서 제안하는 향상된 CABAC 방법이 무손실 화면내 부호화에서 기존의 CABAC 방법에 비해 평균 약 2.41% 의 비트 수를 감소시키는 것을 확인했다.

• IEIE Transactions on Smart Processing and Computing
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• v.6 no.4
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• pp.292-298
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• 2017

The complexity of image compression algorithms has increased in order to improve image compression efficiency. One way to resolve high computational complexity is parallel processing. However, entropy coding, which is lossless compression, does not fit into the parallel processing form because of the correlation between consecutive symbols. This paper proposes a new application-specific instruction set processor (ASIP) platform by adding new context-adaptive binary arithmetic coding (CABAC) instructions to the existing platform to quickly process a variety of entropy coding. The newly added instructions work without conflicts with all other existing instructions of the platform, providing the flexibility to handle many coding standards with fast processing speeds. CABAC software is implemented for High Efficiency Video Coding (HEVC) and the performance of the proposed ASIP platform was verified with a field programmable gate array simulation.