• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.2 s.302
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• pp.143-150
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• 2005

This paper proposes a new $radix-2^4$ FFT algorithm and an efficient pipeline architecture based on this new algorithm for OFDM systems. The pipeline architecture based on the new algorithm has the same number of multipliers as that of the $radix-2^2$ algorithm. However, the multiplier complexity could be reduced by more than $30\%$ by replacing one half of the programmable complex multipliers by the newly proposed CSD constant complex multipliers. From synthesis simulations of a standard 0.35um CMOS Samsung process, a proposed CSD constant complex multiplier achieved more than $60\%$ area efficiency when compared with the conventional programmable complex multiplier. This promoted efficiency can be used for the design of a long length FFT processor in wireless OFDM applications which needs more power and area efficiency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.3
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• pp.698-704
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• 2013

The image process for image enhancement applies differently the same algorithm for each application. So, the optimized value for each application is required. In this paper, the X-ray medical image using a high-pass filter was improved edges. The result image was improved edge and the contrast of flat area using a constant multiplier and offset. Therefore, the high-frequency emphasis filter optimized for medical image is required. These optimized values are the gaussian high-pass filter, the distance of cutoff frequency=0.05 and offset=0.5. From the result of optimaized simulation, The proposed method has enhanced contrast and edge of the image in the contrast of existing mothods.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.5
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• pp.475-480
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• 2018

In OFDM-based systems, FFT is a critical component since it occupies large area and consumes more power. In this paper, we present a low hardware-cost and low power 512-point pipelined FFT design method for OFDM applications. To reduce the number of twiddle factors and to choose simple design architecture, the radix-$2^4-2^3$ algorithm are exploited. For twiddle factor multiplication, we propose a new canonical signed digit (CSD) complex multiplier design method to minimize the hardware-cost. In hardware implementation with Intel FPGA, the proposed FFT design achieves more than about 28% reduction in gate count and 18% reduction in power consumption compared to the previous approaches.

• ETRI Journal
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• v.32 no.1
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• pp.1-10
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• 2010

In this paper, we present a fast Fourier transform (FFT) processor with four parallel data paths for multiband orthogonal frequency-division multiplexing ultra-wideband systems. The proposed 128-point FFT processor employs both a modified radix-$2^4$ algorithm and a radix-$2^3$ algorithm to significantly reduce the numbers of complex constant multipliers and complex booth multipliers. It also employs substructure-sharing multiplication units instead of constant multipliers to efficiently conduct multiplication operations with only addition and shift operations. The proposed FFT processor is implemented and tested using 0.18 ${\mu}m$ CMOS technology with a supply voltage of 1.8 V. The hardware- efficient 128-point FFT processor with four data streams can support a data processing rate of up to 1 Gsample/s while consuming 112 mW. The implementation results show that the proposed 128-point mixed-radix FFT architecture significantly reduces the hardware cost and power consumption in comparison to existing 128-point FFT architectures.

• Bulletin of the Korean Mathematical Society
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• v.55 no.4
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• pp.1137-1147
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• 2018

In this paper, we discovered a sufficient condition ensuring the weighted composition operators $C_{{\omega}_1,{\varphi}_1},{\cdots},C_{{\omega}_N,{\varphi}_N}$ were disjoint supercyclic on $H({\Omega})$ endowed with the compact open topology. Besides, we provided a condition on inducing symbols to guarantee the disjoint supercyclicity of non-constant adjoint multipliers $M^*_{{\varphi}_1},M^*_{{\varphi}_2},{\cdots},M^*_{{\varphi}_N}$ on a Hilbert space ${\mathcal{H}}$.

• Journal of the Korean Mathematical Society
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• v.42 no.3
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• pp.599-619
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• 2005

We define the convolutions of Fourier hyperfunctions and show that every strongly decreasing Fourier hyperfunction is a convolutor for the space of Fourier hyperfunctions and the converse is true. Also we show that there are no differential operator with constant coefficients which have a fundamental solution in the space of strongly decreasing Fourier hyperfunctions. Lastly we show that the space of multipliers for the space of Fourier hyperfunctions consists of analytic functions extended to any strip in $\mathbb{C}^n$ which are estimated with a special exponential function exp$(\mu|\chi|)$.

• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.65-68
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• 2000

It is well-known that the decision rule in the mini-mum mean-squares-error decision feedback equalizer(MMSE-DFE) is biased, and therefore suboptimum with respect to error probability. We present a new family of algorithms that solve the bias problem in the adaptive DFE. A novel constraint, called the constant-norm con-straint, is introduced unifying the quadratic constraint and the monic one. A new cost function based on the constant-norm constraint and Lagrange multiplier is defined. Minimizing the cost function gives birth to a new family of unbiased adaptive DFE. The simula-tion results demonstrate that the proposed method in-deed produce unbiased solution in the presence of noise while keeping very simple both in computation and im-plementation.

• Proceedings of the KIEE Conference
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• 1992.07b
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• pp.1041-1044
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• 1992

A solar cell should be operated at the maximum output point on the I-V characteristic curve with constant current and constant voltage in order that the solar energy be fully utilized. According to, in this paper, we describes a controller which can track the maximum power point of a solar arry using current and voltage ripple variation of step up chopper system. The control circuit is desinged such that actual current and voltage are sensed directly from the solar cell array. These two signal are then holded sampling and multiplies by a single chip multiplier.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.291-292
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• 2006

This paper presents rate-distortion optimization that is considered sequence statistics(complexity) to choose the best macroblock mode decision in H.264. In previous work, Lagrange multiplier is derived by the function of constant value 0.85 and QP so that is not the proper Lagrange multilplier for any image sequence. The proposed algorithm solves the problem by changing constant value 0.85 into adaptive value which is influenced by image complexity, and by reducing the encoder complexity to estimate the image statistics with the multiplication of transformed, quantized rate and distortion. Proposed algorithm is achieved the bit-rate saving up to 5% better than previous method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.6C
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• pp.632-639
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• 2002

To reduce the area and power consumption in constant coefficient multiplications, the constant coefficient can be encoded using canonic signed digit(CSD) representation. When the partial product terms are added depending on the nonzero bit(1 or -1) positions in the CSD-encoded multiplier, all sign bits are properly extended before the addition takes place. In this paper, to reduce the overhead due to sign extension, a new method is proposed based on the fact that carry propagation in the sign extension part can be controlled such that a desired input bit can be propagated as a carry. Also, a fixed-width multiplier design method suitable for CSD multiplication is proposed. As an application, 43-tap filbert transformer for SSB/BPSK-DS/CDMA is implemented. It is shown that, about 16∼28% adders can be saved by the proposed method compared with the conventional methods.