• Journal of Korean Institute of Industrial Engineers
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• v.36 no.3
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• pp.164-175
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• 2010

In this study, we developed a genetic algorithm to find a near optimal solution of concurrent spare parts selection for the operational time period with limited information of weapon systems purchased from overseas. Through the analysis of time profiles related with system operations, we first define the optimization goal which maintains the expected system operating rate under the budget restrictions, and the number of failures and the lead time for each spare part are used to calculate the estimated total down time of the system. The genetic algorithm for CSP selection shows that the objective function minimizes the estimated total down time of systems with satisfying the restrictions. The method provided by this study can be applied to the generalized model of CSP selection for the systems purchased from overseas without provision of their full structure and adequate information.

• The KIPS Transactions:PartA
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• v.17A no.2
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• pp.73-80
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• 2010

As the power of hardware has improved, there have been numerous researches in processing concurrently using multitasking method. The incremental evaluation is the evaluation method of reevaluating only affected parts instead of reevaluating overall program when the program has been changed. It is necessary to do more studies that improve the efficiency of concurrent incremental evaluation to do multitasking using multi-threading of Java not to do in parallel using multiprocessor. In this paper, the dependency in the dependency chart is based on the attribute that describes the real value of the variable that directly affects the semantics, thereby doing efficient evaluation. So using the dependency, this paper presents the concurrent incremental evaluation algorithm for Java Languages and proves its correctness, analyzing the efficiency of concurrent incremental evaluation by the simulation.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.8
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• pp.578-584
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• 2004

The CSVM(Current Support Vector Machine) that is a digital architecture performing all phases of recognition process including kernel computing, learning, and recall of SVM(Support Vector Machine) on a chip is proposed. Concurrent operation by parallel architecture of elements generates high speed and throughput. The classification problems of bio data having high dimension are solved fast and easily using the CSVM. Quadratic programming in original SVM learning algorithm is not suitable for hardware implementation, due to its complexity and large memory consumption. Hardware-friendly SVM learning algorithms, kernel adatron and kernel perceptron, are embedded on a chip. Experiments on fixed-point algorithm having quantization error are performed and their results are compared with floating-point algorithm. CSVM implemented on FPGA chip generates fast and accurate results on high dimensional cancer data.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.477-480
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• 2005

CMA-DD is proposed to improve the steady-state performance of CMA and its performance is depending on switching time between two modes of operation. Castro et al. who proposed a concurrent equalizer for solving problem of CMA-DD, which reduced the sensibility of switching time. However, concurrent algorithm has a problem that it keeps working after convergence. In this paper, we propose concurrent MCMA-DD equalizer combined modified CMA(MCMA) and DD mode for making better concurrent algorithm. The proposed equalizer is better than previous algorithm in convergence speed and steady-state performance. Also, the proposed algorithm decides optimum switching time using residual ISI of the equalizer output.

• Journal of KIISE:Computing Practices and Letters
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• v.10 no.6
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• pp.507-513
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• 2004

In this paper, we consider the methodology of efficient resource usage, specially web clustering system. We develope an algorithm that distributes the load on the web cluster system to use the system resources, such as system memory equally. The response time is chosen as a performance measure on the various clustering models. And based on the concurrent user to the web cluster system, the response time is also examined as the number of users increases. Simulation experience with this algorithm shows that the response time seems to have a good results compare to those with the other algorithm. And, also the effectiveness of clustered system becomes better as long as the number of concurrent user increases. The usage of developed algorithm is more useful when the system consists of many different sub-systems, a heterogeneous clustering system.

• Journal of the Semiconductor & Display Technology
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• v.3 no.4
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• pp.19-27
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• 2004

The characteristic evaluation of A/D converter is to measure the linearity of the converter. The evaluation of the linearity is to measure the DNL, INL, gain error and offset error in the various test parameters of A/D converter. Generally, DNL and INL are to be measured by the Histogram Test Algorithm in the DSP-based ATE environment. And gain error and offset error are to be measured by the calculation equation of the measuring algorithm. It is to propose the new Concurrent Histogram Test Algorithm for the test of the housekeeping A/D converter used in the CDMA cellular phone. Using the proposed method, it is to measure the DNL, INL, gain error and offset error concurrently and to show the measured results.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.10
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• pp.1258-1263
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• 1999

본 논문에서는 CRCW(Concurrent Read Concurrent Write)와 CREW(Concurrent Read Exclusive Write) PRAM(Parallel Random Access Machine) 모델에서 무방향성 그래프 G=(V, E)의 극대 매칭을 구하기 위해 간결한 랜덤 병렬 알고리즘을 제안한다. CRCW PRAM 모델에서 m개의 선을 가진 그래프에 대해, 제안된 매칭 알고리즘은 m개의 프로세서 상에서 {{{{ OMICRON (log m)의 기대 수행 시간을 가진다. 또한 CRCW 알고리즘을 CREW PRAM 모델에서 구현한 CREW 알고리즘은 OMICRON (log^2 m)의 기대 수행 시간을 가지지만,OMICRON (m/logm) 개의 프로세서만을 가지고 수행될 수 있다.Abstract This paper presents simple randomized parallel algorithms for finding a maximal matching in an undirected graph G=(V, E) for the CRCW and CREW PRAM models. The algorithm for the CRCW model has {{{{ OMICRON (log m) expected running time using m processors, where m is the number of edges in G We also show that the CRCW algorithm can be implemented on a CREW PRAM. The CREW algorithm runs in {{{{ OMICRON (log^2 m) expected time, but it requires only OMICRON (m / log m) processors.

• Composites Research
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• v.12 no.6
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• pp.43-52
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• 1999

This paper explains the development of a concurrent engineering system for the rlesign of composite structures. The concurrent engineering system is developed to meet the demand for the better quality products with lower production cost and time. In this study, to compose the architecture of concurrent engineering system, the commercial and noncommercial programs related to design and analysis of composite structures are surveyed and classified. The concurrent engineering system is including various design modules such as design/analysis of composite structures using CLPT and FEM, buckling and post bucking analysis, thermo-elastic analysis of carbon-carbon composite, and optimum design using expert system and genetic algorithm. For the integration and management of softwares, the concurrent engineering system is realized by Microsoft visual $C++{^\circledR}$ that provide multi-tasking and graphic user interface environment.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.8 no.3
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• pp.965-983
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• 2014

Concurrent behaviors of multithreaded programs cannot be described effectively by automata-based models. Thus, concurrent program intrusion attempts cannot be detected. To address this problem, we proposed the process algebra-based detection model for multithreaded programs (PADMP). We generate process expressions by static binary code analysis. We then add concurrency operators to process expressions and propose a model construction algorithm based on process algebra. We also present a definition of process equivalence and behavior detection rules. Experiments demonstrate that the proposed method can accurately detect errors in multithreaded programs and has linear space-time complexity. The proposed method provides effective support for concurrent behavior modeling and detection.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.5
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• pp.149-157
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• 1994

This paper Presents an algorithm for synthesis of sequential statements described at RT level VHDL. The proposed algorithm transforms sequential statements in VHDL into data-flow description consisting of concurrent statements by local and global dependency analysis and output dependency elimination. Transformation into concurrent statements makes it possible to reduce the cost of the synthesized hardwares, thus to get optimal synthesis results that will befit the designer 's intention. This algorithm has been implemented on VSYN and experimental results show that more compact gate-level hardwares are generated compared with Power View system from ViewLogic and Design Analyzer from Synopsys.