• The Transactions of the Korea Information Processing Society
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• v.5 no.11
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• pp.2989-2996
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• 1998

As the circuit density of VLSI grows and its performance improves, delay fault testing of VLSI becomes very important. Delay faults in a circuit can be categorized into two classes, gate delay faults and path delay faults. This paper proposed two methods in dynamic memory usage in the path delay fault simulation. The first method is similar to that used in concurrent fault simulation for stuck-at faults and the second method reduces dynamic memory usage by not inserting a fault descriptor into the fault list when its value is X. The second method, called Implicit-X method, showed superior performance in both dynamic memory usage and simulation time than the first method, called Concurrent-Simulation-Like method.

• The Transactions of the Korea Information Processing Society
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• v.7 no.8
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• pp.2430-2441
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• 2000

A visual concurrent programming environment, called ESTGVP is designed and implemented, which is easy to understand, highly portable, and can represent parallel behaviors. For our purpose, a conventional state transition graph is extended so as to enable both of synchronous and asynchronous parallel operations. We call it extended state transition graph (ESTG). ESTGVP uses the ESTG and texts for programming, and makes it easy programming sequential and parallel behaviors. Also, it is easy to understand the control structure of a program because ESTGVP is a visual programming environment based on the graph. ESTGVP is written in Tel language and thus it is highly portable on various operating systems. It consists of three major components; edition, transformation and execution. If necessary, ESTG can be transformed into C or Tel language, and its execution is based on Tel.

• Journal of Korea Multimedia Society
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• v.20 no.7
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• pp.1073-1089
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• 2017

Changes in the business environment and increased competitiveness have led many companies to consider Business Process Reengineering(BPR) as a means to improve performance. However, while some BPR projects have been successful among the many companies that have performed BPR, most of the reengineering efforts have been deemed unsuccessful as the project failed. There are many answers to this, but the most important point is that the effective linkage between process innovation and information system construction is insufficient. Even if the reform of consciousness is carried out through the promotion of management innovation activities such as BPR, and the process is improved, management infrastructure can not be continuously maintained if infrastructure, especially information system, is not built up to support it. In this paper, we propose BPR and information system combining methodology for successful BPR execution and information system construction, and describe the result of BPR consulting performance when constructing information system and compare the improvement of failure risk factor. In addition, we present the case through the case of K company, and finally present customer satisfaction through post evaluation after completion of K company information system construction project implementation.

• The Transactions of the Korea Information Processing Society
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• v.7 no.4
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• pp.1290-1298
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• 2000

Multimedia Systems such as VOD(Video On Demand) and MOD (Multimedia On Demand) need to support continuous media operations which are randomly called by concurrent users and require that stored media be accessed in real-tim. To satisfy such a requirements, disk arrays consisting of multiple disks are generally used as storage systems. Under the real-time environments to provide users with accessing continuous media in the parallel and concurrent manner, storage systems should be able to deal with user requests independently. In this paper, we present a new fault-tolerant continuous media storage system called PADA(PRR\ulcorner bAsed Disk Array), which is based on a PRR\ulcorner (Prime Round Robin with Grouped Parties) disk placement scheme with enhanced reliability nd load-balancing. We have compared and evaluated the storage space overhead for fault-tolerance, the reliability of diks array systems, the degree of disk load0-balancing, the demanded buffer space, the maximum number of users being capable of supporting and the fault recovery overhead for PADA, RAID 5 and Declustered storage systems. According to the results, PADA is the best among them in that PADA satisfies load-balancing more effectively and servces more user in case of arbitrary-rate retrievals.

• Transactions of Materials Processing
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• v.24 no.5
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• pp.317-322
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• 2015

A process for the concurrent welding and extruding of pipe was designed for continuous production of fin tubes. Unlike a conventional pipe extrusion, the new process is able to extrude a pipe continuously without limit of length by using spring type wire material. The current paper provides the basic research for welding during the extrusion using a spring type wire material. The object of the current study is to investigate the possibility that the spring type wire material could be extrude into a welded pipe. The appropriate extrusion ratio was selected through investigation of loads using computer simulations. As a result, experiments showed that pipe could be welded and simultaneously extruded with spring type wire material of aluminum. The tensile strength of the welded and extruded aluminum pipe can reach 80% of tensile strength of original aluminum feedstock.

• Journal of Korea Game Society
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• v.20 no.5
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• pp.89-98
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• 2020

In MMO game servers, NUMA (Non-Uniform Memory Access) architecture is generally used to achieve high performance. Furthermore, such servers normally use hash tables as internal data structure which have constant time complexity for insert, delete, and search operations. In this study, we proposed a concurrent hash table optimized for NUMA system to make MMO game servers improve their performance. We tested our hash table on 4 socket NUMA system, and the hash table shows at most 100% speedup over another high-performance hash table.

• Journal of Korean Institute of Industrial Engineers
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• v.22 no.3
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• pp.427-440
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• 1996

Constraint networks are a major approach to knowledge representation in Concurrent Engineering (CE) systems. The networks model various factors in CE as constraints linked by shared variables. Many systems have been developed to assist constraint network processing. While these systems can be useful, their underlying assumption that a solution must simultaneously satisfy all the constraints is often unrealistic and hard to achieve. Proposed in this paper is a hierarchical representation of constraint networks using priorities, namely Prioritized Constraint Network (PCN). A mechanism to propagate priorities is developed, and a new satisfiability definition taking into account the priorities is described. Strength of constraint supporters can be derived from the propagated priorities. Several properties useful for investigating PCN's and finding effective solving strategies ore developed.

• IE interfaces
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• v.14 no.1
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• pp.20-29
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• 2001

This paper presents a concurrent design approach that deals with manufacturing cell formation and cellular layout in Cellular Manufacturing System. Manufacturing cell formation is to group machines into machine cells dedicated to manufacture of part families, and cellular layout problem determines layout of the manufacturing cells within shop and layout of the machines within a cell. In this paper, a concurrent approach for design of machine cell and cellular layout is developed considering manufacturing parameters such as alternative process plans, alternative machines, production volume and processing time of part, and cost per unit time of operation. A mathematical model which minimizes total cost consisting of machine installation cost, machine operating cost, and intercell and intracell movements cost of part is proposed. A hybrid method based on genetic algorithm is proposed to solve the manufacturing cell formation and cellular layout design problem concurrently. The performance of the hybrid method is examined on several problems.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1029-1032
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• 1998

In this paper, a comparative study is presented to evaluate the addition architecture of the high-speed checksum module in TCP/IP processing. In order to speed up TCP/IP processing, H/W implementation offers concurrent and parallel processing to yield high speed computation, with respect to S/W implementation. This research aims at comparing two addition architectures of checksum module, which is the major botteleneck in TCP/IP processing. The 16-bit and 8-bit byte-by-byte addition architecture are implemented by the full custom design, and compared, in analytical and experimental manner, from standpoint of space and performance. For LG $0.6\mu\textrm{m}$ TLM process, the 8-bit addition implementation requires the area, 1.3 times larger than the 16-bit one, and it operates at 80MHz while the 16-bit one runs by 66MHz.

• Journal of Electrical Engineering and Technology
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• v.6 no.4
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• pp.573-579
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• 2011

To meet the scalability and performance requirements of data analyses, which often involve voluminous data, efficient parallel or concurrent algorithms and frameworks are essential. We present a high-performance Korean morphological analyzer which employs the MapReduce framework on the graphics processing unit (GPU). MapReduce is a programming framework introduced by Google to aid the development of web search applications on a large number of central processing units (CPUs). GPUs are designed as a special-purpose co-processor. Their programming interfaces are typically formulated for graphics applications. Compared to CPUs, GPUs have greater computation power and memory bandwidth; however, GPUs are more difficult to program because of the design of their architectures. The performance of the Korean morphological analyzer using the MapReduce framework on the GPU is evaluated in comparison with the CPU-based model. The proposed Korean Morphological analyzer shows promising scalable performance on distributed computing with the GPU.