• Journal of KIISE
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• v.43 no.9
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• pp.1015-1025
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• 2016

Currently, software testing is becoming increasingly important in the industrial field and a large body of research supports the improvement of efficient software testing. Model-based testing is generally used to formalize user requirement data for test design. Complex system that includes loop and concurrency has a high probability of path explosion problem. Specially, as threads are added to concurrency, test scenarios have also increased exponentially. However, it is difficult to solve this problem using existing techniques. In this paper, we propose novel path-search technique that focuses on behavioral features of concurrency path in order to avoid path explosion problem. A system that contains concurrent paths is represented by activity diagram in case study section. Efficiency of our study is shown through comparison with several generated test scenarios of other studies. The result indicate that our approach is efficient for finding faults in loop and concurrency with fewer test scenario.

• Journal of Institute of Control, Robotics and Systems
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• v.8 no.9
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• pp.795-802
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• 2002

We present a new dynamic routing scheme for multiple autonomous guided vehicles (AGVs) systems. There have been so many results concerned with scheduling and routing of multiple AGV systems; however, most of them are only applicable to systems with a small number of AGVs under a low degree of concurrency. With an increased number of AGVs in recent applications, these AGV systems are faced with another problem that has never been occurred in a system with a small number AGVs. This is the stop propagation problem. That is, if a leading AGV stops then all the following AGVs must stop to avoid any collision. In order to resolve this problem, we propose a nonstop preferential detour (NPD) algorithm which is a new dynamic routing scheme employing an election algorithm. For real time computation, we introduce two stage control scheme and propose a new path searching scheme, k-via shortest path scheme for an efficient dynamic routing algorithm. Finally, the proposed new dynamic routing scheme is illustrated by an example.

• Journal of KIISE:Databases
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• v.30 no.6
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• pp.641-650
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• 2003

The eXtensible Markup Language(XML) is emerging as a standard format of data representation and exchange on the Internet. There have been researches about storing and retrieving XML documents using the relational database which has techniques in full growth about large data processing, recovery, concurrency control and so on. Since in previous systems same structure information and fundamental operation are used for processing of various kinds of XML queries, only some specific query can be efficiently processed not all types of query. In this paper, we propose a flexible query processing system. To process query efficiently, the proposed system analyzes regular path expression queries, and uses $\theta$-join operation using region numbering values to check ancestor-descendent relationship and equi-join operation using parent's region start value to check parent-child relationship. Thus, the proposed system processes efficiently XML regular path expressions. From the experimental results, we show that proposed XML query processing system is more efficient than previous systems.

• Journal of KIISE:Databases
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• v.27 no.2
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• pp.216-226
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• 2000

This paper suggests a new access path, hashed B-tree which is an efficient access method for integrity checking. Hashed B-tree is based on the observation that most query patterns in enforcing integrity constraints are point queries. Hashed B-tree compresses the key by hashing procedure, which reduces the height of tree and results in fast node search. This method has the advantages such as it can be implemented easily and use the B-tree concurrency control and recovery algorithm with minor modifications.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.11
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• pp.5389-5396
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• 2012

In this paper, an optimized residual data decoder architecture is proposed to improve the performance in H.264/AVC. The proposed architecture is an integrated architecture that combined parallel inverse transform architecture and parallel inverse quantization architecture with common operation units applied new inverse quantization equations. The equations without division operation can reduce execution time and quantity of operation for inverse quantization process. The common operation unit uses multiplier and left shifter for the equations. The inverse quantization architecture with four common operation units can reduce execution cycle of inverse quantization to one cycle. The inverse transform architecture consists of eight inverse transform operation units. Therefore, the architecture can reduce the execution cycle of inverse transform to one cycle. Because inverse quantization operation and inverse transform operation are concurrency, the execution cycle of inverse transform and inverse quantization operation for one $4{\times}4$ block is one cycle. The proposed architecture is synthesized using Magnachip 0.18um CMOS technology. The gate count and the critical path delay of the architecture are 21.9k and 5.5ns, respectively. The throughput of the architecture can achieve 2.89Gpixels/sec at the maximum clock frequency of 181MHz. As the result of measuring the performance of the proposed architecture using the extracted data from JM 9.4, the execution cycle of the proposed architecture is about 88.5% less than that of the existing designs.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.2
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• pp.45-52
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• 2002

In this contributions, we propose a new MSB(most significant bit) algorithm based on AOP(All One Polynomial) and two parallel semi-systolic architectures to computes $AB^2$over finite field $GF(2^m)$. The proposed architectures are based on standard basis and use the property of irreducible AOP(All One Polynomial) which is all coefficients of 1. The proposed parallel semi-systolic architecture(PSM) has the critical path of $D_{AND2^+}D_{XOR2}$ per cell and the latency of m+1. The modified parallel semi-systolic architecture(WPSM) has the critical path of $D_{XOR2}$ per cell and has the same latency with PSM. The proposed two architectures, PSM and MPSM, have a low latency and a small hardware complexity compared to the previous architectures. They can be used as a basic architecture for exponentiation, division, and inversion. Since the proposed architectures have regularity, modularity and concurrency, they are suitable for VLSI implementation. They can be used as a basic architecture for algorithms, such as the Diffie-Hellman key exchange scheme, the Digital Signature Algorithm(DSA), and the ElGamal encryption scheme which are needed exponentiation operation. The application of the algorithms can be used cryptosystem implementation based on elliptic curve.