• 제목/요약/키워드: computer arithmetic

검색결과 252건 처리시간 0.026초

확장논리에 기초한 순차디지털논리시스템 및 컴퓨터구조에 관한 연구 (A Study on Sequential Digital Logic Systems and Computer Architecture based on Extension Logic)

  • 박춘명
    • 한국인터넷방송통신학회논문지
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    • 제8권2호
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    • pp.15-21
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    • 2008
  • 본 논문에서는 2진논리의 확장을 Galis체상에서 해석하여 확장논리에 기초한 순차디지털논리시스템과 컴퓨터구조의 핵심인 연산알고리즘을 논의하였다. 순차디지털논리시스템은 Building Block으로서 T-gate를 사용하였으며, 차순상태함수, 출력함수를 도출하여 최종 궤환이 없는 Moore Model의 순차디지털논리시스템을 구성하였다. 그리고, 컴퓨터구조에서 중요한 연산알고리즘의 핵심인 가산, 감산, 승산 및 제산 알고리즘을 유한체의 수학적 성질을 토대로 각각 도출하였다. 특히, 유한체 GF($P^m$)상에서 P=2인 경우는 기존의 2진디지털논리시스템에 적용이 용이하다는 장점이 있으며, mod2의 성질에 의해 감산 알고리즘은 가산 알고리즘과 동일하다. 제안한 방법은 기존의 2진논리를 확장할 수 있어 좀 더 효율적으로 디지털논리시스템을 구성할 수 있을 것으로 사료된다.

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High Efficient Entropy Coding For Edge Image Compression

  • Han, Jong-Woo;Kim, Do-Hyun;Kim, Yoon
    • 한국컴퓨터정보학회논문지
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    • 제21권5호
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    • pp.31-40
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    • 2016
  • In this paper, we analyse the characteristics of the edge image and propose a new entropy coding optimized to the compression of the edge image. The pixel values of the edge image have the Gaussian distribution around '0', and most of the pixel values are '0'. By using this analysis, the Zero Block technique is utilized in spatial domain. And the Intra Prediction Mode of the edge image is similar to the mode of the surrounding blocks or likely to be the Planar Mode or the Horizontal Mode. In this paper, we make use of the MPM technique that produces the Intra Prediction Mode with high probability modes. By utilizing the above properties, we design a new entropy coding method that is suitable for edge image and perform the compression. In case the existing compression techniques are applied to edge image, compression ratio is low and the algorithm is complicated as more than necessity and the running time is very long, because those techniques are based on the natural images. However, the compression ratio and the running time of the proposed technique is high and very short, respectively, because the proposed algorithm is optimized to the compression of the edge image. Experimental results indicate that the proposed algorithm provides better visual and PSNR performance up to 11 times than the JPEG.

SAR 디스플레이 영상을 위한 무손실 압축 (LOSSLESS DATA COMPRESSION ON SAR DISPLAY IMAGES)

  • Lee, Tae-hee;Song, Woo-jin;Do, Dae-won;Kwon, Jun-chan;Yoon, Byung-woo
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2001년도 제14회 신호처리 합동 학술대회 논문집
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    • pp.117-120
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    • 2001
  • Synthetic aperture radar (SAR) is a promising active remote sensing technique to obtain large terrain information of the earth in all-weather conditions. SAR is useful in many applications, including terrain mapping and geographic information system (GIS), which use SAR display images. Usually, these applications need the enormous data storage because they deal with wide terrain images with high resolution. So, compression technique is a useful approach to deal with SAR display images with limited storage. Because there is some indispensable data loss through the conversion of a complex SAR image to a display image, some applications, which need high-resolution images, cannot tolerate more data loss during compression. Therefore, lossless compression is appropriate to these applications. In this paper, we propose a novel lossless compression technique for a SAR display image using one-step predictor and block arithmetic coding.

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행렬 분해와 공격자 구조를 이용한 비밀이미지 공유 기법 (Secret Image Sharing Scheme using Matrix Decomposition and Adversary Structure)

  • 현승일;신상호;유기영
    • 한국멀티미디어학회논문지
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    • 제17권8호
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    • pp.953-960
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    • 2014
  • In Shamir's (t,n)-threshold based secret image sharing schemes, there exists a problem that the secret image can be reconstructed when an arbitrary attacker becomes aware of t secret image pieces, or t participants are malicious collusion. It is because that utilizes linear combination polynomial arithmetic operation. In order to overcome the problem, we propose a secret image sharing scheme using matrix decomposition and adversary structure. In the proposed scheme, there is no reconstruction of the secret image even when an arbitrary attacker become aware of t secret image pieces. Also, we utilize a simple matrix decomposition operation in order to improve the security of the secret image. In experiments, we show that performances of embedding capacity and image distortion ratio of the proposed scheme are superior to previous schemes.

컴퓨터 생성 홀로그램을 위한 새로운 연산 알고리즘 및 하드웨어 구조 (A New Arithmetic Algorithm and Hardware Architecture for Computer Generated Hologram)

  • 서영호;최현준;유지상;김동욱
    • 한국방송∙미디어공학회:학술대회논문집
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    • 한국방송공학회 2010년도 추계학술대회
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    • pp.302-303
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    • 2010
  • 본 논문에서는 고속으로 홀로그램을 생성하기 위해 새로운 컴퓨터 생성 홀로그램(computer-generated hologram, CGH) 수식을 제안하고, 셀 기반의 VLSI(very large scale integrated circuit) 구조를 제안하였다. 기본 CGH 수식에서 가로 또는 세로 방향의 연산 규칙을 찾아낸 후 가로 또는 세로 방향의 홀로그램 화소를 병렬적으로 구할 수 있는 수식을 유도하였다. 제안한 수식을 바탕으로 초기 파라미터 연산기(initial parameter calculator)와 업데이트-위상 연산기(update-phase calculator)로 구성된 CGH 셀의 구조를 제안하고 하드웨어로 구현하였다. 수식의 변형을 통해서 하드웨어를 간략화 시킬 수 있었고, CGH의 확장을 통해 가로 방향으로 병렬화시킬 수 있는 하드웨어 구조도 보였다. 실험에서는 하드웨어에 사용된 자원을 분석하였다. CGH 커널과 프로세서의 구조는 이전 연구에서 사용된 플랫폼을 그대로 사용하였다.

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휴대 단말기용 3D Graphics Lighting Processor 설계 (A Design of 3D Graphics Lighting Processor for Mobile Applications)

  • 양준석;김기철
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2005년도 추계종합학술대회
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    • pp.837-840
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    • 2005
  • This paper presents 3D graphics lighting processor based on vector processing using pipeline chaining. The lighting process of 3D graphics rendering contains many arithmetic operations and its complexity is very high. For high throughput, proposed processor uses pipelined functional units. To implement fully pipelined architecture, we have to use many functional units. Hence, the number of functional units is restricted. However, with the restricted number of pipelined functional units, the utilization of the units is reduced and a resource reservation problem is caused. To resolve these problems, the proposed architecture uses vector processing using pipeline chaining. Due to its pipeline chaining based architecture, it can perform 4.09M vertices per 1 second with 100MHz frequency. The proposed 3D graphics lighting processor is compatible with OpenGL ES API and the design is implemented and verified on FPGA.

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Flexible Prime-Field Genus 2 Hyperelliptic Curve Cryptography Processor with Low Power Consumption and Uniform Power Draw

  • Ahmadi, Hamid-Reza;Afzali-Kusha, Ali;Pedram, Massoud;Mosaffa, Mahdi
    • ETRI Journal
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    • 제37권1호
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    • pp.107-117
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    • 2015
  • This paper presents an energy-efficient (low power) prime-field hyperelliptic curve cryptography (HECC) processor with uniform power draw. The HECC processor performs divisor scalar multiplication on the Jacobian of genus 2 hyperelliptic curves defined over prime fields for arbitrary field and curve parameters. It supports the most frequent case of divisor doubling and addition. The optimized implementation, which is synthesized in a $0.13{\mu}m$ standard CMOS technology, performs an 81-bit divisor multiplication in 503 ms consuming only $6.55{\mu}J$ of energy (average power consumption is $12.76{\mu}W$). In addition, we present a technique to make the power consumption of the HECC processor more uniform and lower the peaks of its power consumption.

등차수열을 이용한 효율적인 RFID 인증 프로토콜에 관한 연구 (A Study on Efficient RFID Authentication Protocol using Arithmetic Sequence)

  • 강수영;이임영
    • 한국정보처리학회:학술대회논문집
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    • 한국정보처리학회 2006년도 춘계학술발표대회
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    • pp.991-994
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    • 2006
  • 최근 유비쿼터스와 관련하여 핵심 요소 기술로 활용되고 있는 ad-hoc네트워크와 소형 디바이스에 대한 연구가 활발히 진행되고 있다. 이중 소형 디바이스와 관련해 대표적인 기술이 RFID기술이다. RFID 기술의 특징은 주파수 통신을 이용하여 빠른 인식과 데이터 저장이 가능해 기존의 바코드 기술을 대체할수 있는 새로운 형태의 인증 기술이다. 그러나 RFID의 특성상 소형화된 하드웨어와 주파수 통신을 이용할 경우 보안상 많은 취약성이 존재할 수 있다. 따라서 본 논문에서는 기존의 RFID 기술을 분석한 뒤 보안적 취약성을 보완할 수 있는 등차수열을 이용한 안전하고 효율적인 RFID 인증 기술을 제안하고자 한다. 제안된 방식의 경우 등차수열을 이용함으로서 기존의 방식보다 연산량에 따른 효율성을 유지하면서 기존의 방식의 보안 취약성 보완할 수 있는 방식을 제안하고자 한다.

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심박변화율을 이용한 PC 기반 실시간 정신작업부하 측정시스템 개발 (Development of Real-Time Mental Work Load Measurement System using Heart Rate Variability base on Personal Computer)

  • 고한우;윤용현;양희경;김동윤
    • 감성과학
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    • 제4권1호
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    • pp.1-5
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    • 2001
  • The evaluation of mental workload is measured by subjective ratings, physiological signals. It takes long time to analysis the measured signals and is very tedious and time-consumming work. Therefore, to evaluate the affect of workload effectively, real-time measurement system is required. In this paper, real-time mental workload measurement system using cardiac autonomic indiced which reflect well the mental workload was developed and evaluated. Analyzed indices were HR, IBI, Lorentz plot, CSI, CVI, and LF/HF ratio of heart rate variability. The system was applied to evaluate the affect of arithmetic task and showed good results. This system was consisted of ECG amplifier, A/D converter, and personal computer, and algorithm was implemented using LabVIEW.

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Collapsing effects in numerical simulation of chaotic dynamical systems

  • Daimond, P.;Kloeden, P.;Pokrovskii, A.;Suzuki, M.
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 1994년도 Proceedings of the Korea Automatic Control Conference, 9th (KACC) ; Taejeon, Korea; 17-20 Oct. 1994
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    • pp.753-757
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    • 1994
  • In control system design, whether the various subsystems are in discrete time or continuous time, the state space is usually regarded as a continuum. However, when the system is implemented, some subsystems may have a state space which is a subset of finite computer arithmetic. This is an important concern if a subsystem has chaotic behaviour, because it is theoretically possible for rich and varied motions in a continuum to collapse to trivial and degenerate behaviour in a finite and discrete state space [5]. This paper discusses new ways to describe these effects and reports on computer experiments which document and illustrate such collapsing behaviour.

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