• Journal of the Institute of Convergence Signal Processing
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• v.2 no.3
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• pp.93-101
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• 2001

In this paper, we propose an image downscaler used in multimedia video applications, such as DTV, TV-PIP, PC-video, camcorder, videophone and so on. The proposed image downscaler provides a scaled image of high-quality and high-performance. This paper will explain the scaling theory using two-dimensional digital filters. It is the method that removes an aliasing noise and decreases the hardware complexity, compared with Pixel-drop and Upsamling. Also, this paper will prove it improves scaling precisians and decreases the loss of data, compared with the Scaler32, the Bt829 of Brooktree, and the SAA7114H of Philips. The proposed downscaler consists of the following four blocks: line memory, vertical scaler, horizontal scaler, and FIFO memory. In order to reduce the hardware complexity, the using digital filters are implemented by the multiplexer-adder type scheme and their all the coefficients can be simply implemented by using shifters and adders. It also decreases the loss of high frequency data because it provides the wider BW of 6MHz as adding the compensation filter. The proposed downscaler is modeled by using the Verilog-HDL and the model is verified by using the Cadence simulator. After the verification is done, the model is synthesized into gates by using the Synopsys. The synthesized downscaler is Placed and routed by the Mentor with the IDEC-C632 0.65${\mu}{\textrm}{m}$ library for further IC implementation. The IC master is fixed in size by 4,500${\mu}{\textrm}{m}$$\times$4,500${\mu}{\textrm}{m}$. The active layout size of the proposed downscaler is 2,528${\mu}{\textrm}{m}$$\times$3,237${\mu}{\textrm}{m}$.

• The Transactions of the Korean Institute of Power Electronics
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• v.4 no.1
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• pp.26-34
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• 1999

According to increase of nonlinear power electronics equipment, active power filters have been researched and developed for many years to compensate harmonic disturbances and reactive power. However the commercial of active power filter is being proceeded slowly, because the cost of active power filter compared to the passive filter for harmonic and reactive power compensation is expensive. Especially, the use of DSP (Digital Signal Processing) chip, which is frequently used to control 3-phase active power filter, is a factor of increasing the cost of active power filters. On the other hand, the use of only analog controller makes the controller's circuits much more complicate and depreciates the flexibilities of controller. In this paper, a controller with low cost for 5[kVA] 3-phase active power filter system is designed. To reduce the expense of active filter system, the presented controller is composed of digital control part using Intel 80C196KC $\mu$P and analog control part using hysteresis controller for current control. Characteristic analysis of designed controller for active filter system is performed by computer simulation and compensating characteristics of the designed controller are verified by experiment.tegy can apply to the vector control, leading to better output torque capability in the ac motor drive system. This strategy is that in the overmodulation range, the d-axis output current is given a priority to regulate the flux well, instead the q-axis output curent is sacrificed. Therefore, the vector control even in the overmodulation PWM operation can be achieved well. For this purpose, the d-axis output voltage of a current controller to control the flux is conserved. the q-axis output voltage to control the torque is controlled to place the reference voltage vector on the hexagon boundary in case of the overmodulation. The validity of the proposed overall scheme is confirmed by simulation and experiments for a 22[kW] induction motor drive system.

• Journal of Broadcast Engineering
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• v.14 no.2
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• pp.144-153
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• 2009

Recently, as the necessity of a light-weighted video encoding technique has been rising for applications such as UCC(User Created Contents) or Multiview Video, Distributed Video Coding(DVC) where a decoder, not an encoder, performs the motion estimation/compensation taking most of computational complexity has been vigorously investigated. Wyner-Ziv coding reconstructs an image by eliminating the noise on side information which is decoder-side prediction of original image using channel code. Generally the side information of Wyner-Ziv coding is generated by using frame interpolation between key frames. The channel code such as Turbo code or LDPC code which shows a performance close to the Shannon's limit is employed. The noise model of Wyner-Ziv coding for channel decoding is called Virtual Channel Noise and is generally modeled by Laplacian or Gaussian distribution. In this paper, we propose a Wyner-Ziv coding method based on the frequency-adaptive channel noise modeling in transform domain. The experimental results with various sequences prove that the proposed method makes the channel noise model more accurate compared to the conventional scheme, resulting in improvement of the rate-distortion performance by up to 0.52dB.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.148-156
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• 2013

This paper suggests a multi-level and multi-output SMPS based on a shared digital logic controller through independently operating in each dedicated time periods. Although the shared architecture can be devised with small area and high efficiency, it has critical drawbacks that real-time control of each DPWM generators are impossible and its output voltage can be unstable. To solve these problems, a real-time current compensation scheme is proposed as a solution. A current consumption of the core block and entire block with four driver buffers was simulated about 4.9mA and 30mA at 10MHz switching frequency and 100MHz core operating frequency. Output voltage ripple was 11 mV at 3.3V output voltage. Over/undershoot voltage was 10mV/19.6mV at 3.3V output voltage. The noise performance was simulated at 800mA and 100KHz load regulation. Core circuit can be implemented small size in $700{\mu}m{\times}800{\mu}m$ area. For the verification of proposed circuit, the simulations were carried out with Dong-bu Hitek BCD $0.35{\mu}m$ technology.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.1
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• pp.13-20
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• 2004

In this paper, we have analyzed the current MPEG-4 video encoding tools and proposed efcient coding techniques that reduce the complexity of the encoder. Until recently, encoder optimization without shape coding has been a major concern in video for wire/wireless low bit rate coding services. Recently, we found out that the computational complexity of MPEG-4 shape coding plays a very important role in the object-based coding through experiments. We have made an experiment whether we could get optimized object-based coding method through successfully combining latest optimized texture coding techniques with our proposed optimized shape coding techniques. In texture coding, we applied the MVFAST method for motion estimation. We chose not to use IVOPF(Intelligent VOP Formation) but to use TRB(Tightest Rectangular Boundary) for positioning VOP and, finally, to eliminate the spiral search of shape motion estimation to reduce the complexity in shape coding. As a result of experiment, our proposed scheme achieved improved time complexity over the existing reference software by $57.3\%$ and over the optimized method on which only shape coding was applied by $48.7\%$, respectively.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.5
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• pp.62-70
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• 2007

In this paper, the boost Power Factor Correction(PFC) technique for Direct Torque Control(DTC) of brushless DC motor drive in the constant torque region is implemented on a TMS320F2812DSP. Unlike conventional six-step PWM current control, by properly selecting the inverter voltage space vectors of the two-phase conduction mode from a simple look-up table at a predefined sampling time, the desired quasi-square wave current is obtained, therefore a much faster torque response is achieved compared to conventional current control. Furthermore, to eliminate the low-frequency torque oscillations caused by the non-ideal trapezoidal shape of the actual back-EMF waveform of the BLDC motor, a pre-stored back-EMF versus position look-up table is designed. The duty cycle of the boost converter is determined by a control algorithm based on the input voltage, output voltage which is the dc-link of the BLDC motor drive, and inductor current using average current control method with input voltage feed-forward compensation during each sampling period of the drive system. With the emergence of high-speed digital signal processors(DSPs), both PFC and simple DTC algorithms can be executed during a single sampling period of the BLDC motor drive. In the proposed method, since no PWM algorithm is required for DTC or BLDC motor drive, only one PWM output for the boost converter with 80 kHz switching frequency is used in a TMS320F2812 DSP. The validity and effectiveness of the proposed DTC of BLDC motor drive scheme with PFC are verified through the experimental results. The test results verify that the proposed PFC for DTC of BLDC motor drive improves power factor considerably from 0.77 to as close as 0.9997 with and without load conditions.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.2
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• pp.72-77
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• 2009

In this paper, a 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial data communication without the reference clock is described This CDR circuit consists of 5 parts as Phase and frequency detector(PD and FD), multi-phase Voltage Controlled-Oscillator(VCO), Charge-pumps (CP) and external Loop-Filter(KF). It is adapted the PD and FD, which incorporates a half-rate bang-bang type oversampling PD and a half-rate FD that can improve pull-in range. The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the tuning range and tuning linearity. Each delay cell has output buffers as a full-swing generator and a duty-cycle mismatch compensation. This materialized CDR can achieve wide pull-in range without an extra reference clock and it can be also reduced chip area and power consumption effectively because there is no additional Phase Locked- Loop(PLL) for generating reference clock. The CDR circuit was designed for fabrication using 0.18um 1P6M CMOS process and total chip area excepted LF is $1{\times}1mm^2$. The pk-pk jitter of recovered clock is 26ps at 3.2Gb/s input data rate and total power consumes 63mW from 1.8V supply voltage according to simulation results. According to test result, the pk-pk jitter of recovered clock is 55ps at the same input data-rate and the reliable range of input data-rate is about from 2.4Gb/s to 3.4Gb/s.

• Journal of Energy Engineering
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• v.26 no.4
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• pp.107-117
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• 2017

Since South Korea started to apply Renewable Portfolio Standard (RPS) in 2012, there have been huge investment for deploying renewable technologies. Recently, the government determined to incentivize battery energy storage system(BESS) with renewable generations in order to induce the improvement of dispatching capability. In this paper, the annual pattern of PV generation based on actual generation data in South Korea is analyzed and the duration curve of capacity factor is proposed in order to provide the simplified analyzing methodology of present support policy for additional BESS installation for decision maker who is responsible for supply and demand planning. With suggested methodology, the range of appropriate BESS size with respect to the variation of system marginal price(SMP) and renewable energy certificate(REC) price can be derived briefly, and decision makers easily evaluate the effect of support scheme. Current policy for BESS installation support present additional BESS-related installation policy may give incentives to developers partially, however, the dependence between BESS size and benefit components (SMP and REC) can limit the deployment of the various portfolios of the BESS. Therefore, when improving the current policy in future, addressing the dependence between the technical aspects of battery size and the benefit components separately by the technical and economical parts is needed to set the suitable compensation rules for the renewable generation and BESS.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.49 no.2
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• pp.35-44
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• 2012

Most recent infrared (IR) sensors have a focal-plane array (FPA) structure. Spatial non-uniformity of a FPA structure, however, introduces unwanted fixed pattern noise (FPN) to images. This non-uniformity correction (NUC) of a FPA can be categorized into target-based and scene-based approaches. In a target-based approach, FPN can be separated by using a uniform target such as a black body. Since the detector response randomly drifts along the time axis, however, several scene-based algorithms on the basis of a video sequence have been proposed. Among those algorithms, the state-of-the-art one based on Kalman filter uses one-directional warping for motion compensation and only compensates for offset non-uniformity of IR camera detectors. The system model using one-directional warping cannot correct the boundary region where a new scene is being introduced in the next video frame. Furthermore, offset-only correction approaches may not completely remove the FPN in images if it is considerably affected by gain non-uniformity. Therefore, for FPN reduction in IR videos, we propose a joint correction algorithm of gain and offset based on bi-directional warping. Experiment results using simulated and real IR videos show that the proposed scheme can provide better performance compared with the state-of-the art in FPN reduction.

• The KIPS Transactions:PartC
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• v.16C no.1
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• pp.65-72
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• 2009

Due to the popularity of mobile devices and advances in wireless communication technologies, a mobile ad hoc network has received a lot of attention. In the existing data replication management research, the use of a replica has been shown to be an efficient technique for improving data accessibility. However, to use a replica in ad hoc networks, the data consistency between the original data and the replica should be guaranteed. In the traditional research, a mobile node should check an original data whether the data is updated or not. However, It may be costly or sometimes impossible to check the original data. In the case of the time constraint applications, the checking cost can cause more serious problem. In this paper, we propose the time-guarantee based cache invalidation schemes for time constraint applications and the threshold based compensation method to enhance the time-guarantee based scheme. The proposed schemes can remove the "rollback" problem. Simulation results show that our schemes outperform the previous ones in terms of access time with little loss of data currency.