• Journal of Digital Convergence
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• v.11 no.11
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• pp.415-420
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• 2013

U-WHS refers to a means of remote health monitoring service to combine fitness with wellbing. U-WHS is a system which can measure and manage biometric information of patients without any limitation on time and space. In this paper, we performed in order to look into the influence that the encryption module influences on the communication evaluation in the biometric information transmission gone to the smart mobile device and Hospital Information System.In the case of the U-WHS model, the client used the Objective-c programming language for software development of iOS Xcode environment and SEED and HIGHT encryption module was applied. In the case of HIS, the MySQL which is the Websocket API of the HTML5 and relational database management system for the client and inter-server communication was applied. Therefore, in WIFI communication environment, by using wireshark, data transfer rate of the biometric information, delay and loss rate was checked for the evaluation.

• International Journal of Computer Science & Network Security
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• v.23 no.6
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• pp.27-34
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• 2023

This paper proposed an Inter-Carrier-Interference (ICI) Canceling Orthogonal Frequency Division Multiplexing (OFDM) receiver for 5G mobile system to support 500 km/h linear motor high speed terrestrial transportation service. A receiver in such high-speed train sees the transmission channel which is composed of multiple Doppler-shifted propagation paths. Then, a loss of sub-carrier orthogonality due to Doppler-spread channels causes ICI. The ICI Canceler is realized by the following three steps. First, using the Demodulation Reference Symbol (DMRS) pilot signals, it analyzes three parameters such as attenuation, relative delay, and Doppler-shift of each multi-path component. Secondly, based on the sets of three parameters, Channel Transfer Function (CTF) of sender sub-carrier number 𝒏 to receiver sub-carrier number 𝒍 is generated. In case of 𝒏≠𝒍, the CTF corresponds to ICI factor. Thirdly, since ICI factor is obtained, by applying ICI reverse operation by Multi-Tap Equalizer, ICI canceling can be realized. ICI canceling performance has been simulated assuming severe channel condition such as 500 km/h, 2 path reverse Doppler Shift for QPSK, 16QAM, 64QAM and 256QAM modulations. In particular, for modulation schemes below 16QAM, we confirmed that the difference between BER in a 2 path reverse Doppler shift environment and stationary environment at a moving speed of 500 km/h was very small when the number of taps in the multi-tap equalizer was set to 31 taps or more. We also confirmed that the BER performance in high-speed mobile communications for multi-level modulation schemes above 64QAM is dramatically improved by the use of a multi-tap equalizer.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.6
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• pp.622-634
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• 2013

The circuit level implementation of nanoscale Insulated Shallow Extension Silicon On Nothing (ISE-SON) MOSFET has been investigated and compared with the other conventional devices i.e. Insulated Shallow Extension (ISE) and Silicon On Nothing (SON) using the ATLAS 3D device simulator. It can be observed that ISE-SON based inverter shows better performance in terms of Voltage Transfer Characteristics, noise margin, switching current, inverter gain and propagation delay. The reliability issues of the various devices in terms of supply voltage, temperature and channel length variation has also been studied in the present work. Logic circuits (such as NAND and NOR gate) and ring oscillator are also implemented using different architectures to illustrate the capabilities of ISE-SON architecture for high speed logic circuits as compared to other devices. Results also illustrates that ISE-SON is much more temperature resistant than SON and ISE MOSFET. Hence, ISE-SON enables more aggressive device scaling for low-voltage applications.

• Journal of Korea Multimedia Society
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• v.18 no.2
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• pp.189-198
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• 2015

Despite the fact that traffic engineering techniques have been comprehensively utilized in the past to enhance the performance of communication networks, the distinctive characteristics of Software Defined Networking (SDN) demand new traffic engineering techniques for better traffic control and management. Considering the behavior of traffic, large flows normally carry out transfers of large blocks of data and are naturally packet latency insensitive. However, small flows are often latency-sensitive. Without intelligent traffic engineering, these small flows may be blocked in the same queue behind megabytes of file transfer traffic. So it is very important to identify large flows for different applications. In the scope of this paper, we present an approach to detect large flows in real-time without even a short delay. After the detection of large flows, the next problem is how to control these large flows effectively and prevent network jam. In order to address this issue, we propose an approach in which when the controller is enabled, the large flow is mitigated the moment it hits the predefined threshold value in the control application. This real-time detection, marking, and controlling of large flows will assure an optimize usage of an overall network.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.12
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• pp.2675-2680
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• 2010

Computation steps for 3D graphic processing consist of two stages - fixed operation stage and programming required stage. Using this characteristic of 3D pipeline, a hybrid structure between graphics hardware designed by fixed structure and programmable hardware based on instructions, can handle graphic processing more efficiently. In this paper, fragment Shader is designed under this hybrid structure. It also supports OpenGL ES 2.0. Interior interface is optimized to reduce the delay of entire pipeline, which may be occurred by data I/O between the fixed hardware and the Shader. Interior register group of the Shader is designed by an interleaved structure to improve the register space and processing speed.

• Journal of Korea Multimedia Society
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• v.22 no.8
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• pp.913-922
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• 2019

The Internet of Things (IoT) envisions smart objects collecting and sharing data at a massive scale via the Internet. One challenging issue is how to disseminate data to relevant data consuming objects efficiently. In such a massive IoT network, Mission critical data dissemination imposes constraints on the message transfer delay between objects. Due to the low power and communication range of IoT objects, data is relayed over multi-hops before arriving at the destination. In this paper, we propose a quorum-based adaptive dissemination algorithm (QADA) for the critical data in the monitoring-based applications of massive IoTs. To design QADA, we first design a new stepped-triangular grid structures (sT-grid) that support data dissemination, then construct a triangular grid overlay in the fog layer on the lower IoT layer and propose the data dissemination algorithm of the publish/subscribe model that adaptively uses triangle grid (T-grid) and sT-grid quorums depending on the mission critical in the overlay constructed to disseminate the critical data, and evaluate its performance as an analytical model.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.1
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• pp.45-57
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• 2005

In this paper, we extend the performance of bidirectional TCP connection over end-to-end network that uses transfer rate-based flow and congestion control. The sharing of a common buffer by TCP packets and acknowledgement has been known to result in an effect called ack compression, where acks of a connection arrive at the source bunched together, resulting in unfairness and degraded throughput. The degradation in throughput due to bidirectional traffic can be significant. Even in the simple case of symmetrical connections with adequate window size, the connection efficiency is improved about 20% for three levels of background traffic 2.5Mbps, 5.0Mbps and 7.5Mbps. Otherwise, the throughput of jitter is reduced about 50% because round trip delay time is smaller between source node and destination node. Also, we show that throughput curve is improved with connection rate algorithm which is proposed for TCP congetion avoidance as a function of aggressiveness threshold for three levels of background traffic 2.5Mbps, 5Mbps and 7.5Mbps. By analyzing the periodic bursty behavior of the source IP queue, we derive estimated for the maximum queue size and arrive at a simple predictor for the degraded throughput, applicable for relatively general situations.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.2
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• pp.696-702
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• 2010

In many industrial applications, it is very important to control the temperature of the controlled object to the target temperature as closely as possible. Although it is apparent that the great obstacles in controller design are time-delay of the thermal responses of the controlled object and the effect of thermal interference between neighboring heating zones, one more fundamental obstacle is a very large amount of time which is required during repeated experiments in controller design process. Therefore, a convenient simulation environment, which can represent thermal behavior accurately within appropriate time, is needed. In this paper, a prototype of 2D FEM (finite element method) heat transfer simulation environment using MATLAB is constructed to be usefully adopted into industrial applications with temperature controller design.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.6
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• pp.1166-1174
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• 2004

In this paper, a design of RISC-based transmission wrapper processor for TCP/IP protocol stack is described. The processor consists of input and output buffer memory with dual bank structure, 32-bit RISC microprocessor core, DMA unit with on-the-fly checksum capability, and memory module. To handle the various modes of TCP/IP protocol, hardware-software codesign approach based on RISC processor is used rather than the conventional state machine design. To eliminate large delay time due to sequential executions of data transfer and checksum operation, DMA module which can execute the checksum operation along with data transfer operation is adopted. The designed processor exclusive of variable-size input/output buffer consists of about 23,700 gates and its maximum operating frequency is about 167MHz under 0.35${\mu}m$ CMOS technology.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.321-327
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• 2006

This paper presents low power and high frequency design of instructions using ad-hoc techniques at transistor level for full custom and semi-custom ASIC(Application Specific Integrated Circuit) designs. The proposed design has been verified at high level using Verilog-HDL and simulated using ModelSim for the logical correctness. It is then observed at the layout level using LASI using $0.25{\mu}m$ technology and analyzed for timing characteristic under Win-spice simulation environment. The result shows the significant reduction up to $35\%$ in the power consumption by any general purpose processor like RISC or CISC. A significant reduction in the propagation delay is also observed. increasing the frequency for the fetch and execute cycle for the CPU, thus increasing the overall frequency of operation.