• Title/Summary/Keyword: communication latency

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Performance Analysis of Single and Multiple Bus Topology Due to Master and Slave (마스터와 슬레이브에 따른 싱글버스와 다중버스 토폴로지의 성능분석)

  • Lee, Kook-Pyo;Yoon, Yung-Sup
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.9
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    • pp.96-102
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    • 2008
  • The SoC bus topology is classified to single and multiple bus systems due to bus number. In single bus system, the selected only one master among the masters that try to initiate the bus transaction can execute its data transaction. On the other hand, in multiple bus system, as several buses that can be operated independently are connected with bridge, multiple data can be transferred parallel in each bus. However, In the case of data communication from one bus system to the other, data latency has remarkably increased in multiple bus. Furthermore, the performance of multiple bus can be easily different from master number, slave type and so on. In this paper, the performance of single and multiple bus architecture is compared and quantitatively analysed with the variation of master number and slave type especially a tying SDRAM, SRAM and register with TLM simulation method.

TFT-LCD Controller Implementation Using DMA of High Performance in Multi-Bus Architecture (다중버스 아키텍처 구조에서 고성능 DMA를 이용한 TFT-LCD Controller 구현)

  • Lee, Kook-Pyo;Lee, Keun-Hwan;Yoon, Yung-Sup
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.8
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    • pp.54-60
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    • 2008
  • The bus architecture consists of a master initiating a communication transaction, a slave responding to the transaction, a arbiter selecting a master, a bridge connecting buses and so on. Recently this is more complicated and developed toward multi-bus architecture. In this paper, several cases of multi-shared bus architecture are discussed and in order to decrease the bridge latency, the architecture introducing a memory selector is proposed. Finally, a LCD controller using DMA master is integrated in this bus architecture that is verified due to RTL simulation and FPGA board test. DMA, LCD line buffer and SDRAM controller are normally operated in the timing simulation using ModelSim tool, and the LCD image is confirmed in the real FPGA board containing LCD panel.

Effects of LDPCA Frame Size for Parity Bit Estimation Methods in Fast Distributed Video Decoding Scheme (고속 분산 비디오 복호화 기법에서 패리티 비트 예측방식에 대한 LDPCA 프레임 크기 효과)

  • Kim, Man-Jae;Kim, Jin-Soo
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.16 no.8
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    • pp.1675-1685
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    • 2012
  • DVC (Distributed Video Coding) technique plays an essential role in providing low-complexity video encoder. But, in order to achieve the better rate-distortion performances, most DVC systems need feedback channel for parity bit control. This causes the DVC-based system to have high decoding latency and becomes as one of the most critical problems to overcome for a real implementation. In order to overcome this problem and to accelerate the commercialization of the DVC applications, this paper analyzes an effect of LDPCA frame size for adaptive LDPCA frame-based parity bit request estimations. First, this paper presents the LDPCA segmentation method in pixel-domain and explains the temporal-based bit request estimation method and the spatial-based bit request estimation method using the statistical characteristics between adjacent LDPCA frames. Through computer simulations, it is shown that the better performance and fast decoding is observed specially when the LDPCA frame size is 3168 in QCIF resolution.

A Cell Loading Algorithm for Realtime Navigation in the Web-Based Virtual Space (웹기반 가상공간에서 실시간 네비게이션을 위한 셀 로딩 알고리즘)

  • Lee, Ki-Dong;Ha, Ju-Han
    • The KIPS Transactions:PartB
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    • v.11B no.3
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    • pp.337-344
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    • 2004
  • Most of the virtual space constructed sufficiently realistic need a lot of memory space to navigate smoothly. And this kind of virtual space also requires real-time responsibility for the navigation as well as realism. In the off-line virtual system, real-time responsibility can be resolved by using large scale if secondary memory. In the web-based online virtual system, on the other hand, real-time responsibility is highly related to the latency time of network data communication. This induces the necessity of the algorithm for fast data loading. In this paper, we propose and verify the validity of the two methodology for cell leading algorithm. According to the results of computer simulation, the algorithm using hexagonal type cell promotes the real-time responsibility over 30% than that of the rectangular type.

Efficient Group Management Mechanism and Architecture for Secure Multicast (안전한 멀티캐스트 서비스 제공을 위한 효율적인 그룹 관리 메커니즘 및 구조)

  • Eun, Sang-A;Jo, Tae-Nam;Chae, Gi-Jun;Lee, Sang-Ho;Park, Won-Ju;Na, Jae-Hun
    • The KIPS Transactions:PartC
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    • v.9C no.3
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    • pp.323-330
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    • 2002
  • Multicast services are gradually diversified and used widely. Proportionately, they become the center of attackers' attention and there are growing possibilities of an intelligence leak. Therefore, research related to secure multicast should be required to provide multicast service efficiently. This paper presents the architecture for secure multicast which provides efficient group management mechanism in group consists using member's dynamic join and leave. This architecture can provide secure multicast services to many users with regard to security aspects in one-to-many communication. The simulation results show that the proposed architecture achieves an efficient group management and a secure data transmission with low latency compared with the other existing secure multicast architecture.

Satellite Mobility Pattern Scheme for Centrical and Seamless Handover Management in LEO Satellite Networks

  • Tuysuz, Aysegul;Alagoz, Fatih
    • Journal of Communications and Networks
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    • v.8 no.4
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    • pp.451-460
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    • 2006
  • Since low earth orbit (LEO) satellite constellations have important advantages over geosynchronous earth orbit (GEO) systems such as low propagation delay, low power requirements, and more efficient spectrum allocation due to frequency reuse between satellites and spotbeams, they are considered to be used to complement the existing terrestrial fixed and wireless networks in the evolving global mobile network. However, one of the major problems with LEO satellites is their higher speed relative to the terrestrial mobile terminals, which move at lower speeds but at more random directions. Therefore, handover management in LEO satellite networks becomes a very challenging task for supporting global mobile communication. Efficient and accurate methods are needed for LEO satellite handovers between the moving footprints. In this paper, we propose a new seamless handover management scheme for LEO satellites (SeaHO-LEO), which utilizes the handover management schemes aiming at decreasing latency, data loss, and handover blocking probability. We also present another interesting handover management model called satellite mobility pattern based handover management in LEO satellites (PatHO-LEO) which takes mobility pattern of both satellites and mobile terminals into account to minimize the handover messaging traffic. This is achieved by the newly introduced billboard manager which is used for location updates of mobile users and satellites. The billboard manager makes the proposed handover model much more flexible and easier than the current solutions, since it is a central server and supports the management of the whole system. To show the performance of the proposed algorithms, we run an extensive set of simulations both for the proposed algorithms and well known handover management methods as a baseline model. The simulation results show that the proposed algorithms are very promising for seamless handover in LEO satellites.

SHA-1 Pipeline Configuration According to the Maximum Critical Path Delay (최대 임계 지연 크기에 따른 SHA-1 파이프라인 구성)

  • Lee, Je-Hoon;Choi, Gyu-Man
    • Convergence Security Journal
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    • v.16 no.7
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    • pp.113-120
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    • 2016
  • This paper presents a new high-speed SHA-1 pipeline architecture having a computation delay close to the maximum critical path delay of the original SHA-1. The typical SHA-1 pipelines are based on either a hash operation or unfolded hash operations. Their throughputs are greatly enhanced by the parallel processing in the pipeline, but the maximum critical path delay will be increased in comparison with the unfolding of all hash operations in each round. The pipeline stage logics in the proposed SHA-1 has the latency is similar with the result of dividing the maximum threshold delay of a round by the number of iterations. Experimental results show that the proposed SHA-1 pipeline structure is 0.99 and 1.62 at the operating speed ratio according to circuit size, which is superior to the conventional structure. The proposed pipeline architecture is expected to be applicable to various cryptographic and signal processing circuits with iterative operations.

User Signature Protection Model for Different Cloud Areas (이질적인 클라우드 환경에 적합한 사용자 서명 보호 모델)

  • Jeong, Yoon-Su;Kim, Yong-Tae;Park, Gil-Cheol
    • Journal of the Korea Convergence Society
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    • v.10 no.12
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    • pp.23-28
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    • 2019
  • Cloud services are services developed to serve a wider variety of users in different fields. However, although cloud services are designed to reflect the needs of different users, a variety of security damages resulting from them are increasing and technologies are needed to address them. This paper proposes a user signature management model that prevents third parties from exploiting the user's signature in a heterogeneous cloud The proposed model strengthens the functionality of the intermediate devices that make up the hierarchical cloud while also managing the signature information of the partitioned user. As a result of the performance assessment, the proposed model not only distributed user signature management, but also improved efficiency by 8.5% on average because intermediate devices distributed user signature processing, and reduced the user's signature latency by 13.3% on average when performing user authentication processing. On average, the overhead generated by intermediate devices processing a user's signature was 10.1 percent lower than that of conventional techniques.

Energy-Efficient Resource Allocation for Application Including Dependent Tasks in Mobile Edge Computing

  • Li, Yang;Xu, Gaochao;Ge, Jiaqi;Liu, Peng;Fu, Xiaodong
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.14 no.6
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    • pp.2422-2443
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    • 2020
  • This paper studies a single-user Mobile Edge Computing (MEC) system where mobile device (MD) includes an application consisting of multiple computation components or tasks with dependencies. MD can offload part of each computation-intensive latency-sensitive task to the AP integrated with MEC server. In order to accomplish the application faultlessly, we calculate out the optimal task offloading strategy in a time-division manner for a predetermined execution order under the constraints of limited computation and communication resources. The problem is formulated as an optimization problem that can minimize the energy consumption of mobile device while satisfying the constraints of computation tasks and mobile device resources. The optimization problem is equivalently transformed into solving a nonlinear equation with a linear inequality constraint by leveraging the Lagrange Multiplier method. And the proposed dual Bi-Section Search algorithm Bi-JOTD can efficiently solve the nonlinear equation. In the outer Bi-Section Search, the proposed algorithm searches for the optimal Lagrangian multiplier variable between the lower and upper boundaries. The inner Bi-Section Search achieves the Lagrangian multiplier vector corresponding to a given variable receiving from the outer layer. Numerical results demonstrate that the proposed algorithm has significant performance improvement than other baselines. The novel scheme not only reduces the difficulty of problem solving, but also obtains less energy consumption and better performance.

Performance Evaluation and Optimization of Dual-Port SDRAM Architecture for Mobile Embedded Systems (모바일 내장형 시스템을 위한 듀얼-포트SDRAM의 성능 평가 및 최적화)

  • Yang, Hoe-Seok;Kim, Sung-Chan;Park, Hae-Woo;Kim, Jin-Woo;Ha, Soon-Hoi
    • Journal of KIISE:Computing Practices and Letters
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    • v.14 no.5
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    • pp.542-546
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    • 2008
  • Recently dual-port SDRAM (DPSDRAM) architecture tailored for dual-processor based mobile embedded systems has been announced where a single memory chip plays the role of the local memories and the shared memory for both processors. In order to maintain memory consistency from simultaneous accesses of both ports, every access to the shared memory should be protected by a synchronization mechanism, which can result in substantial access latency. We propose two optimization techniques by exploiting the communication patterns of target applications: lock-priority scheme and static-copy scheme. Further, by dividing the shared bank into multiple blocks, we allow simultaneous accesses to different blocks thus achieve considerable performance gain. Experiments on a virtual prototyping system show a promising result - we could achieve about 20-50% performance gain compared to the base DPSDRAM architecture.