• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.05a
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• pp.304-307
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• 2015

Virtualization lacks capabilities for enabling the application to scale efficiently because of new applications components which are raised to be configured on demand. In this paper, we propose an architecture that affords mobile app based on nomadic smartphone using not only mobile cloud computing-cloudlet architecture but also a dedicated platform that relies on using virtual private mobile networks to provide reliable connectivity through Long Term Evolution (LTE) wireless communication. The design architecture lies with how the cloudlet host discovers service and sends out the cloudlet IP and port while locating the user mobile device. We demonstrate the effectiveness of the proposed architecture by implementing an android application responsible of real time analysis by using a vehicle to applications smart phones interface approach that considers the smartphones to act as a remote users which passes driver inputs and delivers outputs from external applications.

• Journal of the Korean housing association
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• v.17 no.1
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• pp.37-45
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• 2006

The purpose of this study is to explore the spacial boundary in Kazuyo Sejima's housing architecture, to give attention to contemporary housing architecture that we inhabit, and to escape from existing architectural concepts. This study seeks to the meaning and possibility of the spacial boundary on the basis of contemporary architecture. The spacial boundary can be studied in the aspect of architectural space that molds human experience and perception. As a result of this study, three properties in the spacial boundary are revealed. One property of the spacial boundary is soft that protect privacy from gaze of exterior. Another property is that communication that changes according to material of boundary and its experience of observer. The other property is to have uncertainty by compound of programs and material-mixing senses including its perception. This results means that the spacial boundary as interface which is represent our everyday life in the contemporary housing architecture.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.2067-2070
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• 2002

In this paper, a VLSI architecture for transform and quantization module, which consists of 2D-DCT, quantization, AC/DC prediction block, scan conversion, inverse quantization and 2D-IDCT, is presented. The architecture of the module is designed to handle a macroblock data within 1064 cycles and suitable for MPEG-4 video codec handling CIF image formats. Only single 1-D DCT/IDCT cores are used for the design instead of 2-D DCT/IDCT, respectively. 1-bit serial distributed arithmetic architecture is adopted for 1-D DCT/IDCT to reduce the hardware area in this architecture. As the result, the maximum utilization of hardware can be achieved, and power consumption can be minimized. The proposed design is operated on 27MHz clock. The experimental results show that the accuracy of DCT and IDCT meet the IEEE specification.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.381-382
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• 2006

In this paper, we present an efficient architecture for connected speech recognition that can be efficiently implemented with FPGA. The architecture consists of newly derived two-level dynamic programming (TLDP) that use only bit addition and shift operations. The advantages of this architecture are the spatial efficiency to accommodate more words with limited space and the computational speed from avoiding propagation delays in multiplications. The architecture is highly regular, consisting of identical and simple processing elements with only nearest-neighbor communication, and external communication occurs with the end processing elements.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.3
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• pp.327-335
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• 2008

As communication is becoming increasingly prevalent and especially communication architecture is more relying on the open standard communication protocols, the security issues become major concerns. In this paper we consider possible cyber attacks in the applications based on the current distribution communication architecture, and then derive the security goals. Next we propose how the security algorithms can be adapted to achieve these security goals. We intend to adapt the most efficient ways of secure message exchange, taking the resource-constrained FRTUs into account Finally we show some experiments to validate the protocols.

• Journal of the Optical Society of Korea
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• v.19 no.1
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• pp.45-54
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• 2015

In this study, a novel parallel wavefront correction system architecture is proposed, and a model-based tabu search (MBTS) algorithm is introduced for this new system to compensate wavefront aberration caused by atmospheric turbulence in a free-space optical (FSO) communication system. The algorithm flowchart is presented, and a simple hypothetical design for the parallel correction system with multiple adaptive optical (AO) subsystems is given. The simulated performance of MBTS for an AO-FSO system is analyzed. The results indicate that the proposed algorithm offers better performance in wavefront aberration compensation, coupling efficiency, and convergence speed than a stochastic parallel gradient descent (SPGD) algorithm.

• Journal of information and communication convergence engineering
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• v.3 no.2
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• pp.76-79
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• 2005

In this paper, a low-complexity maximum-likelihood (ML) decoder based on QR decomposition, called real-valued LCMLDec decoder or RVLCMLDec for short, is proposed for the Vertical Bell Labs Layered Space-Time (V-BLAST) architecture, a promising candidate for providing high data rates in future fixed wireless communication systems [1]. Computer simulations, in comparison with other detection techniques, show that the proposed decoder is capable of providing the V­BLAST schemes with ML performance at low detection complexity

• Journal of Navigation and Port Research
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• v.32 no.1
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• pp.37-45
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• 2008

The research on an E-Navigation(E-Nav) strategy development has recently carried out by the IMO sub-committee on safety of navigation(NAV). The design of communication system architecture is a key factor in the E-Nav strategy development and it may drive the direction of a national R&D project on future navigational and marine communication systems. This study aims at designing a standard model of E-Nav communication network architecture, which enhances navigational safety and provides additional benefits in marine transportation. To achieve this purpose, authors have suggested E-Nav services, which are divided into five categories, i.e., safety and security, maritime meteorology, distress, business, and infotainment, by analyzing the related user requirements. As results, this paper proposes the E-Nav communication network architecture that consists of the navigation and communication equipments.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38B no.2
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• pp.130-139
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• 2013

In recent, the communication networks of wind power farm are becoming crucial technologies for monitoring and controlling the large-scale offshore wind power farm. In this paper, EPON based communication network architectures are proposed in order to combat the problems of conventional Ethernet based communication network such as delay, data processing overhead and the fairness of data transmission among turbines in offshore wind power farm. The proposed architecture constructs the point to multi-point network by using OLT and ONUs installed in central control center and wind turbines respectively. The EPON based communication network architecture has low cost, high reliability, and fair transmission capability. To evaluate the performance of proposed architectures, the wind power farm based on IEC 61850 is modelled by using OPNET The simulation results are analyzed and compared with conventional Ethernet based communication network in terms of the overhead, delay and fairness of data transmission.

• Journal of Electrical Engineering and Technology
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• v.4 no.4
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• pp.559-565
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• 2009

Power dissipation during scan testing is becoming an important concern as design sizes and gate densities increase. The high switching activity of combinational circuits is an unnecessary operation in scan shift mode. In this paper, we present a novel architecture to reduce test power dissipation in combinational logic by blocking signal transitions at the logic inputs during scan shifting. We propose a unique architecture that uses dmuxed scan flip-flop (DSF) and transmission gate as an alternative to muxed scan flip-flop. The proposed method does not have problems with auto test pattern generation (ATPG) techniques such as test application time and computational complexity. Moreover, our elegant method improves performance degradation and large overhead in terms of area with blocking logic techniques. Experimental results on ITC99 benchmarks show that the proposed architecture can achieve an average improvement of 30.31% in switching activity compared to conventional scan methods. Additionally, the results of simulation with DSF indicate that the powerdelay product (PDP) and area overhead are improved by 28.9% and 15.6%, respectively, compared to existing blocking logic method.