• Journal of Power Electronics
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• v.12 no.4
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• pp.548-558
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• 2012

In this paper, a novel offset-based single-state pulse width modulation (PWM) method for achieving zero common-mode voltage (CMV) and reducing switching losses in multilevel inverters is presented. The specific active switching state of the zero common-mode (ZCM) voltage that approximates the reference voltage can be deduced from the switching state sequence of the reduced CMV phase disposition PWM (CMV PD PWM) method. From the reference leg voltages for the zero common-mode voltage, an N-to-2-level transformation defines a virtual two-level inverter and the corresponding nominal leg voltage references. The commutation process of the reduced CMV PD PWM method in a multilevel inverter and its outputs can be simply followed in a nominal switching time diagram for the virtual inverter. The characteristics of the reduced CMV PD PWM and the single-state PWM for zero common-mode voltage are analyzed in detail in this paper. The theoretical analysis of the proposed PWM method is verified by experimental results.

• Journal of Power Electronics
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• v.19 no.3
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• pp.727-743
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• 2019

This paper presents a pulse-width modulation strategy to eliminate the common mode voltage (CMV) with reduced CMV spikes in multilevel inverters since a high CMV magnitude and its fast variations dv/dt result in bearing failure of motors, overvoltage at motor terminals, and electromagnetic interference (EMI). The proposed method only utilizes the zero CMV states in a space vector diagram and it is implemented by a carrier-based pulse-width modulation (CBPWM) method. This method is generalized for odd number levels of inverters including neutral-point-clamped (NPC) and cascaded H-bridge inverters. Then it is extended to the over-modulation mode. The over-modulation mode is implemented by using the two-limit trajectory principle to maintain linear control and to avoid look-up tables. Even though the CMV is eliminated, CMV spikes that can cause EMI and bearing current problems still exist due to the deadtime effect. As a result, the deadtime effect is analyzed. By taking the deadtime effect into consideration, the proposed method is capable of reducing CMV spikes. Simulation and experimental results verify the effectiveness of the proposed strategy.

• Journal of Power Electronics
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• v.16 no.1
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• pp.142-152
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• 2016

Common mode voltage (CMV) generation is a major problem in switching power converter fed induction motor drive systems. CMV is the zero sequence voltage generated due to the switching action of power converters. Even a small magnitude of CMV with a high rate of change may circulate large bearing currents which may damage a machine's bearings and shorten its life. There are several methods of controlling CMV. This paper presents 3-level sinusoidal pulse width modulation based techniques to control the magnitude and rate of change of CMV in multilevel AC-DC-AC drive systems. Simulation and experimental investigations have been presented to validate the performance of proposed technique to control CMV in 3-level neutral point clamped inverter based AC-DC-AC system.

• Journal of Power Electronics
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• v.19 no.6
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• pp.1477-1485
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• 2019

This paper proposes an effective model predictive current control (MPCC) that involves using 10 virtual voltage vectors to reduce the current harmonics and common-mode voltage (CMV) for a two-level five-phase voltage source inverter (VSI). In the proposed scheme, 10 virtual voltage vectors are included to reduce the CMV and low-order current harmonics. These virtual voltage vectors are employed as the input control set for the MPCC. Among the 10 virtual voltage vectors, two are applied throughout the whole sampling period to reduce current ripples. The two selected virtual voltage vectors are based on location information of the reference voltage vector, and their duration times are calculated using a simple algorithm. This significantly reduces the computational burden. Simulation and experimental results are provided to verify the effectiveness of the proposed scheme.

• Proceedings of the KIPE Conference
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• 2015.11a
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• pp.209-210
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• 2015

This paper presents a new model predictive control method without the effect of a weighting factor in order to reduce common-mode voltage (CMV) for a three-phase voltage source inverter (VSI). By utilizing two active states with same dwell time during a sampling period instead of one state used in conventional method, the proposed method can reduce the CMV of VSI without the weighting factor. Simulation is carried out to verify the effectiveness of the proposed predictive control method with the aid of PSIM software.

• Journal of Power Electronics
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• v.14 no.6
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• pp.1197-1207
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• 2014

Common-mode voltage (CMV) causes overvoltage stress to winding insulation and damages AC motors. CMV with high dv/dt causes leakage currents, which create noise problems for equipment installed near the converter. This study proposes a new pulse-width modulation (PWM) strategy for three-level T-type NPC inverters. This strategy substantially eliminates CMV. The principle for selecting suitable triangle carrier signals for the three-level T-type NPC is described. The proposed method can mitigate the peak value of CMV by 50% compared with the phase disposition pulse-width modulation method. Furthermore, the proposed method exhibits better harmonic spectrum and lower root mean square value for the CMV than those of the reduced-CMV method on the basis of the phase opposition disposition PWM scheme with modulation index higher than 0.5. The proposed modulation can easily be implemented using software without any additional hardware modifications. Both simulation and experimental results demonstrate that the proposed carrier phase-shift PWM method has good output waveform performance and reduces CMV.

• Journal of Power Electronics
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• v.11 no.1
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• pp.21-27
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• 2011

In this paper, an approach to reduce common-mode voltage (CMV) at the output of multilevel inverters using a phase opposition disposed (POD) sinusoidal pulse width modulation (SPWM) technique is proposed. The SPWM technique does not require computations therefore, this technique is easy to implement on-line in digital controllers. A good tradeoff between the quality of the output voltage and the magnitude of the CMV is achieved in this paper. This paper realizes the implementation of a POD-SPWM technique to reduce CMV using a five-level diode clamped inverter for a three phase induction motor. Experimental and simulation results demonstrate the feasibility of the proposed technique.

• Journal of Power Electronics
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• v.17 no.4
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• pp.923-932
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• 2017

This paper proposes a novel scheme which can compensate the common-mode voltage (CMV) for five-level active neutralpoint clamped (5L-ANPC) inverters, which is based on modifying the space vector pulse width modulation (SVPWM) and adding an auxiliary leg to the inverter. For the modified SVPWM, only the 55 voltage vectors producing low CMV values among the 125 possible voltage vectors are utilized, which varies over the three voltage levels of $-V_{dc}/12$, 0 V, and $V_{dc}/12$. In addition, the compensating voltage, which is injected into the 5L-ANPC inverter system to cancel the remaining CVM through a common-mode transformer (CMT) is generated by the additional NPC leg. By the proposed method, the CMV of the inverter is fully eliminated, while the utilization of the DC-link voltage is not decreased at all. Furthermore, all of the DC-link and flying capacitor voltages of the inverter are well controlled. Simulation and experimental results have verified the validity of the proposed scheme.

• Journal of Power Electronics
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• v.15 no.6
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• pp.1524-1532
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• 2015

Conventional space vector pulse width modulation based asymmetrical dual inverter configuration produces high common mode voltage (CMV) variations. This CMV causes the flow of common mode current, which adversely affects the motor bearings and electromagnetic interference of nearby electronic systems. In this study, a simple and generalized carrier based pulse width modulation (PWM) technique is proposed for dual inverter configuration. This simple approach generates various continuous and discontinuous modulating signals based PWM algorithms. With the application of the discontinuous modulating signal based PWM algorithm to the asymmetrical dual inverter configuration, the CMV can be reduced with a slightly improved quality of output voltage. The performance of the continuous and discontinuous modulating signals based PWM algorithms is explored through both theoretical and experimental studies. Results show that the discontinuous modulating signal based PWM algorithm efficiently reduces the CMV and switching losses.

• Journal of Power Electronics
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• v.17 no.1
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• pp.88-95
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• 2017

To reduce common-mode voltage (CMV), various reduced CMV pulse width modulation (RCMV-PWM) algorithms have been proposed, including active zero state PWM (AZSPWM) algorithms, remote state PWM (RSPWM) algorithms, and near state PWM (NSPWM) algorithms. Among these algorithms, AZSPWM algorithms can reduce CMV, but they increase the number of switchings compared to the conventional space vector PWM (CSVPWM). This paper presents a new AZSPWM algorithm for reductions in both the CMV and total number of switchings in BLAC motor drives. Since the proposed AZSPWM algorithm uses only active voltage vectors for motor control, it reduces CMV by 1/3 compared to CSVPWM. The proposed AZSPWM algorithm also reduces the total number of switchings compared to existing AZSPWM algorithms by eliminating the switchings required from one sector to the next. The performance of the proposed algorithm is verified by analyses, simulations, and experimental results.