• Journal of the Institute of Electronics Engineers of Korea SP
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• v.43 no.1 s.307
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• pp.101-108
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• 2006

In this paper, an efficient butterfly structure for Radix-4 FFT algorithm using DA(Distributed Arithmetic) is proposed. It is shown that DA can be efficiently used in twiddle factor calculation of the Radix-4 FFT algorithm. The Verilog-HDL coding results for the proposed DA butterfly structure show $61.02\%$ cell area reduction comparison with those of the conventional multiplier butterfly structure. furthermore, the 64-point Radix-4 pipeline structure using the proposed butterfly and delay commutators is compared with other conventional structures. Implementation coding results show $46.1\%$ cell area reduction. Due to its efficient processing scheme, the proposed FFT structure can be widely used in large size of FFT like OFDM Modem.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.2C
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• pp.172-181
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• 2010

In this paper, we propose an adaptive block quantization method. The propose method perfrect reconstructs side information without high complexity in the encoder side, as transmitting motion vectors from a decoder to an encoder side. Also, at the encoder side, residual signals between reconstructed side information and original frame are adaptively quantized to minimize parity bits to be transmitted to the decoder. The proposed method can effectively allocate bits based on bit error rate of side information. Also, we can achieved bit-saving by transmission of parity bits based on the error correction ability of the LDPC channel decoder, because we can know bit error rate and positions of error bit in encoder side. Experimental results show that the proposed algorithm achieves bit-saving by around 66% and delay of feedback channel, compared with the convntional algorithm.

• The Journal of the Acoustical Society of Korea
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• v.36 no.1
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• pp.70-77
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• 2017

Bandwidth extension is a technique to improve speech quality, intelligibility and naturalness, extending from the 300 ~ 3,400 Hz narrowband speech to the 50 ~ 7,000 Hz wideband speech. In this paper, an Artificial Bandwidth Extension (ABE) module embedded in the Opus audio decoder is designed using the information of narrowband speech to reduce the computational complexity of LPC (Linear Prediction Coding) and LSF (Line Spectral Frequencies) analysis and the algorithm delay of the ABE module. We proposed a spectral envelope extension method using DBN (Deep Belief Network), one of deep learning techniques, and the proposed scheme produces better extended spectrum than the traditional codebook mapping method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.10
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• pp.67-74
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• 2007

Turbo code, a kind of channel coding technique, has ben used in the field of digital mobile communication system if the number of iterations is increased in the several channel environments, my further iteration results in very little improvement, and requires much delay and computation in proportion to the number of iterations. In this paper, it proposes an efficient stopping rules for the iteration process in turbo decoding. By using absolute mean values for the LLR difference values between the first and second decoder in the present decoding process, the proposed algorithm can largely reduce the average number of iterations without BER performance degradation in all SNR regions. As a result of simulation, the average number of iterations of proposed algorithm is reduced by about $18.25%{\sim}20.58%$ compared to SDR algerian in the lower SNR region, and is reduced by about $22.96%{\sim}28.74%$ compared to method using variance values of extrinsic information in the upper SNR region.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.3
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• pp.103-110
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• 2008

In this paper, an efficient butterfly structure for 8K/2K-Point Radix-4 FFT algorithm using CORDIC(coordinate rotation digital computer) is proposed. It is shown that CORDIC can be efficiently used in twiddle factor calculation of the Radix-4 FFT algorithm. The Verilog-HDL coding results for the proposed CORDIC butterfly structure show 36.9% cell area reduction comparison with those of the conventional multiplier butterfly structure. Furthermore, the 8K/2K-point Radix-4 pipeline structure using the proposed butterfly and delay commutators is compared with other conventional structures. Implementation coding results show 11.6% cell area reduction. Due to its efficient processing scheme, the proposed FFT structure can be widely used in large size of FFT like OFDM Modem.

• Journal of Satellite, Information and Communications
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• v.5 no.1
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• pp.43-47
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• 2010

In future mobile networks, hybrid/integrated satellite and terrestrial systems will play an important role. Most of the mobile communication systems are focused on the terrestrial systems, in this case, compatibilities between the satellite and terrestrial systems are very important for efficiency of the systems. Terrestrial systems of all the 4G mobile communication adopted the adaptive modulation and coding (AMC) schemes for efficient usage of resources, and the updating interval of resource allocation in an order of msec. However, because of the long round trip delay of satellite systems, we cannot employ the same AMC scheme specified for the terrestrial system, and thus it cannot effectively counteract to short term fadings. In the paper, we propose the method to apply AMC to mobile satellite systems. In addition, in order to effectively counteract to short term fadings, we present the simulation results of the AMC combined with an interleaver.

• Journal of Satellite, Information and Communications
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• v.7 no.1
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• pp.65-74
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• 2012

The QoS guarantee for the forward link in satellite communication networks is very important because there are a variety of packets with multiplexing. Especially, the packets are processed depending on the available bandwidth in satellite network changing the wireless channel state in accordance with weather condition. The DVB-S2 increases the transmission efficiency by applying the adaptive coding and modulation (ACM) techniques as a countermeasure of rain attenuations. However, the channel estimation algorithm is required to support the ACM techniques that select the MODCOD values depending on the feedback data transmitted by RCSTs(Return Channel via Satellite Terminal) because satellite communication networks have a long propagation delay. In this paper, we proposed the channel estimation algorithm using rain attenuation values and reference data and the packet scheduling scheme to support the QoS and fairness. As a result of performance evaluation, we showed that proposed algorithm exactly predicts the channel conditions and supports bandwidth fairness to the individual RCST and guarantees QoS for user traffics.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.10C
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• pp.923-929
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• 2003

Turbo processing have been known as methods close to Shannon limit in the aspect of wireless multi-input multi-output (MIMO) communications similarly to wireless single antenna communication. The iterative processing can maximize the mutual effect of coding and interference cancellation, but LDPC coding has not been used for turbo processing because of the inherent decoding process delay. This paper suggests a LDPC coded MIMO system with turbo parallel space-time (Turbo-PAST) processing for high-speed wireless communications and proposes a average soft-output syndrome (ASS) check scheme at low signal to noise ratio (SNR) for the Turbo-PAST system to decide the reliability of decoded frame. Simulation results show that the suggested system outperforms conventional system and the proposed ASS scheme effectively reduces the amount of turbo processing iterations without performance degradation from the point of average number of iterations.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.8
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• pp.4077-4091
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• 2017

This paper presents the design of a broadcasting scenario and system for an 8K-resolution content. Due to an 8K content is four times larger than the 4K content in terms of size, many technologies such as content acquisition, video coding, and transmission are required to deal with it. Therefore, high-quality video and audio for 8K (ultra-high definition television) service is not possible to be transmitted only using the current terrestrial broadcasting system. The proposed broadcasting system divides the 8K content into four 4K contents by area, and each area is hierarchically encoded by Scalable High-efficiency Video Coding (SHVC) into three layers: L0, L1, and L2. Every part of the 8K video content divided into areas and hierarchy is independently treated. These parts are transmitted over heterogeneous networks such as digital broadcasting and broadband networks after going through several processes of generating signal messages, encapsulation, and packetization based on MPEG media transport. We propose three methods of generating streams at the sending entity to merge the divided streams into the original content at the receiving entity. First, we design the composition information, which defines the presentation structure for displays. Second, a descriptor for content synchronization is included in the signal message. Finally, we define the rules for generating "packet_id" among the packet header fields and design the transmission scheduler to acquire the divided streams quickly. We implement the 8K broadcasting system by adapting the proposed methods and show that the 8K-resolution contents are stably received and serviced with a low delay.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.1
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• pp.33-39
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• 2007

Finite field multipliers are the basic building blocks in many applications such as error-control coding, cryptography and digital signal processing. Hence, the design of efficient dedicated finite field multiplier architectures can lead to dramatic improvement on the overall system performance. In this paper, a new bit serial structure for a multiplier with low latency in Galois field is presented. To speed up multiplication processing, we divide the product polynomial into several parts and then process them in parallel. The proposed multiplier operates standard basis of $GF(2^m)$ and is faster than bit serial ones but with lower area complexity than bit parallel ones. The most significant feature of the proposed architecture is that a trade-off between hardware complexity and delay time can be achieved.