• Journal of KIISE
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• v.41 no.12
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• pp.1018-1025
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• 2014

An ROP attack creates gadget sequences which consist of existing code snippets in a program, and hijacks the control flow of a program by chaining and executing gadget sequences consecutively. Existing defense schemes have limitations in that they cause high execution overhead, an increase in the binary size overhead, and a low applicability. In this paper, we solve these problems by introducing zero-sum defender, which is a fast and space-efficient mitigation scheme against ROP attacks. We find a fundamental property of gadget execution in which control flow starts in the middle of a function without a call instruction and ends with a return instruction. So, we exploit this property by monitoring whether the execution is abused by ROP attacks. We achieve a very low runtime overhead with a very small increase in the binary size. In our experimental results, we verified that our defense scheme prevents real world ROP attacks, and we showed that there is only a 2% performance overhead and a 1% binary size increase overhead in several benchmarks.

• KIPS Transactions on Computer and Communication Systems
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• v.2 no.5
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• pp.217-222
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• 2013

Return-Oriented Programming(ROP) is an advanced code-reuse attack like a return-to-libc attack. ROP attacks combine gadgets in program code area and make functions like a Turing-complete language. Some of previous defense methods against ROP attacks show high performance overhead because of dynamic execution flow analysis and can defend against only certain types of ROP attacks. In this paper, we propose Indirect Branch Target Address Verification (IBTAV). IBTAV detects ROP attacks by checking if target addresses of indirect branches are valid. IBTAV can defends against almost all ROP attacks because it verifies a target address of every indirect branch instruction. Since IBTAV does not require dynamic execution flow analysis, the performance overhead of IBTAV is relatively low. Our evaluation of IBTAV on SPEC CPU 2006 shows less than 15% performance overhead.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.17 no.1
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• pp.100-113
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• 2018

The Proximity Service, which is one of the most popular network capacity improvement methods, uses the frequency reuse in order to increase the frequency efficiency. As a result, inter-cell interference between cellular and proximity service users occurs at a cell edge. In this paper, we proposed a mitigation scheme for inter-cell interference, where we suggested a new function of and eNB with ProSe function exchanging information about ProSe parameters and ProSe user equipment with neighboring cells via the X2 interface. As the first step, the resource which did not cause the inter-cell interference problem were pre-allocated through the frequency sensing in the ProSe direct discovery. As the next step, the inter-cell interference problem was solved by reallocating appropriate resources based on the ProSe application code, the ProSe application QoS, the ProSe application ID and validity timer in ProSe direct communication.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.27 no.1
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• pp.76-86
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• 2023

Radars used by air-crafts have two important characteristics; First, they should have a real-time signal processing system finishing signal processing before deadline while getting and processing successive in-phase and quadrature data. Second, they can cover a lot of modes including A2A(Air to Air), A2G(Air to Gound), A2S(Air to Sea), and Ground Map(GM). So the structure of radar signal processing SWs in modern airborne radars are becoming more complicate. Also, the implementation of radar signal processing SW needs to reuse common code blocks between other modes for efficiency or change some of the code blocks into alternative algorithm blocks. These are the reason why the radar signal processing SW framework suggested in this paper is taking advantage of modular programming. This paper proposes an modular framework applicable on the airborne radar signal processing SW maintaining the real-time characteristic using the signal processing procedures for A2G/A2S as examples.

• Journal of the Korea Society of Computer and Information
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• v.29 no.2
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• pp.119-126
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• 2024

The IISS(Integrated Interface Storage System) software performs the function of transmitting tactical domain messages of Combat Management System for interface analysis of Naval Combat System. The source code is relatively large because the IISS software handles most messages. The modifications of source code of the IISS software occur frequently due to changes in interconnected equipment and messages. Therefore, additional effort and cost are required during the development process. In this paper, we studied standardization of the IISS software to improve reusability. Through the feature model, the components of the IISS software were divided by function and modification elements were separated. And the structure of the IISS software was improved by applying design patterns. As a result, it was possible to minimize modifications of the IISS software by changes in interconnected equipment and messages and a reduction in development costs could be expected.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.28 no.3
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• pp.643-653
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• 2018

Xamarin is a representative cross-platform development framework that allows developers to write mobile apps in C# for multiple mobile platforms, such as Android, iOS, or Windows Phone. Using Xamarin, mobile app developers can reuse existing C# code and share significant code across multiple platforms, reducing development time and maintenance costs. Meanwhile, malware authors can also use Xamarin to spread malicious apps on more platforms, minimizing the time and cost of malicious app creation. In order to cope with this problem, it is necessary to analyze and detect malware written with Xamarin. However, little studies have been conducted on static analysis methods of the apps written in Xamarin. In this paper, we examine the structure of Android apps written with Xamarin and propose a static analysis technique for the apps. We also demonstrate how to statically reverse-engineer apps that have been transformed using code obfuscation. Because the Android apps written with Xamarin consists of Java bytecode, C# based DLL libraries, and C/C++ based native libraries, we have studied static reverse engineering techniques for these different types of code.

• Journal of IKEEE
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• v.18 no.3
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• pp.341-348
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• 2014

When several resuable semiconductor IPs are connected and implemented into an integrated chip, each semiconductor IP should provide code files for synthesis and interface modeling files for simulation and verification. However, description methods and levels of abstraction of interface modeling files are different because these semiconductor IPs are designed by different designers, which makes some problems in simulation and verification. This paper proposes a standardized modeling method of semiconductor IP interfaces. It restricts semiconductor IP interfaces to several predefined level of abstraction. The proposed method helps the chip integration designer to easily connect different semiconductor IPs and to simulate and verify them.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.11
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• pp.2404-2410
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• 2011

This paper describes the design overview of cluster file system $SANique^{TM}$ based on SAN(Storage Area Network) environment. The design issues and problems of the conventional global buffer manager are also illustrated under a large set of clustered computing hosts. We propose the efficient global buffer management method that provides the more scalability and availability. In our proposed global buffer management method, we reuse the maintained list of lock information from our cluster lock manager. The global buffer manger can easily find and determine the location of requested data block cache based on that lock information. We present the pseudo code of the global buffer manager and illustration of global cache operation in cluster environment.

• The KIPS Transactions:PartA
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• v.12A no.1 s.91
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• pp.1-6
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• 2005

This paper presents a new algorithm on low power survivor path memory implementation of the trace-back systolic array Viterbi algorithm. A novel idea is to reuse the already-generated trace-back routes to reduce the number of trace-back operations. And the spurious switching activity of the trace-back unit is reduced by making use of a clock gating method. Using the SYNOPSYS power estimation tool, DesignPower, our experimental result shows the average $40{\%}$ power reduction and $23{\%}$ area increase against the trace-back unit introduced in [1].

• KIISE Transactions on Computing Practices
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• v.23 no.5
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• pp.304-309
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• 2017

Programmers use multiple languages to reuse legacy code best suited to their problems. However, it is quite challenging to develop error-free multilingual programs because new types of bugs occur since misunderstanding about language interfaces such as Java Native Interface (JNI) and Python/C. There is a considerable amount of research to overcome multilingual program bugs and errors but these researches have less consideration about substantiality of programming languages, language interfaces, and bugs to evaluate their analyses and tools. In this paper, we have identified and establish substantiality of multilingual programming research with empirical study about diversity and interoperability of programming languages in Ubuntu software ecosystem based on real-world statistical data.