• Journal of the Institute of Electronics Engineers of Korea SP
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• v.37 no.5
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• pp.84-93
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• 2000

The conventional fractal decoding was implemented to IFS(iterated function system) for every range regions But a part of the range regions can be decoded without the iteration and there is a data dependence regions In order to decode $R{\times}R$ range blocks, It needs $2R{\times}2R$ domain blocks This decoding can be analyzed to the dependence graph The vertex of the graph represents the range blocks, and the vertex is classified into the vertex of the range and domain The edge indicates that the vertex is referred to the other vertices The in-degree and the out-degree are defined to the number of the edge that is entered and exited, respectively The proposed method is analyzed by a dependence graph to the fractal code, and the decoding order is recomposed by the information of the out-degree That is, If the out-degree of the vertex is zero, then this vertex can be used to the vertex with data dependence Thus, the proposed method can extend the data dependence regions by the recomposition of the decoding order As a result, the Iterated regions are minimized without loss of the image quality or PSNR(peak signal-to-noise ratio), Therefore, it can be a fast decoding by the reducing to the computational complexity for IFS in the fractal Image decoding.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.1
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• pp.22-30
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• 2011

In this paper, we propose a memory efficient multi-rate Low Density Parity Check (LDPC) decoder for China Mobile Multimedia Broadcasting (CMMB). We find the best trade-off between the performance and the circuit area by designing a partially parallel decoder which is capable of passing multiple messages in parallel. By designing an efficient address generation unit (AGU) with an index matrix, we could reduce both the amount of memory requirement and the complexity of computation. The proposed regular LDPC decoder was designed in Verilog HDL and was synthesized by Synopsys' Design Compiler using Chartered $0.18{\mu}m$ CMOS cell library. The synthesized design has the gate size of 455K (in NAND2). For the two code rates supported by CMMB, the rate-1/2 decoder has a throughput of 14.32 Mbps, and the rate-3/4 decoder has a throughput of 26.97 Mbps. Compared with a conventional LDPC for CMMB, our proposed design requires only 0.39% of the memory.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.11
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• pp.2594-2603
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• 1997

A novel method of adaptive beam forming is presented in this paper. The proposed technique provides for a suboptimal beam pattern that increases the Signal to Noise/Interference Ratio (SNR/SIR), thus, eventually increases the capacity of the communication channel, under an assumption that the desired signal is dominant compared to each component of interferences at the receiver, which is precoditionally achieved in Code Division Multiple Access (CDMA) mobile communications by the chip correlator. The main advantages of the new technique are:(1)The procedure requires neither reference signals nor training period, (2)The signal interchoerency does not affect the performance or complexity of the entire procedure, (3)The number of antennas does not have to be greater than that of the signals of distinct arrival angles, (4)The entire procedure is iterative such that a new suboptimal beam pattern be generated upon the arrival of each new data of which the arrival angle keeps changing due tot he mobility of the signal source, (5)The total amount of computation is tremendously reduced compared to that of most conventional beam forming techniques such that the suboptimal beam pattern be produced at vevery snapshot on a real-time basis. The total computational load for generating a new set of weitht including the update of an N-by-N(N is the number of antenna elements) autocovariance matrix is $0(3N^2 + 12N)$. It can further be reduced down to O(11N) by approximating the matrix with the instantaneous signal vector.

• International Journal of High-Rise Buildings
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• v.1 no.1
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• pp.37-51
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• 2012

New generation of tall and complex buildings systems are now introduced that are reflective of the latest development in materials, design, sustainability, construction, and IT technologies. While the complexity in design is being overcome by the availability and advances in structural analysis tools and readily advanced software, the design of these buildings are still reliant on minimum code requirements that yet to be validated in full scale. The involvement of the author in the design and construction planning of Burj Khalifa since its inception until its completion prompted the author to conceptually develop an extensive survey and real-time structural health monitoring program to validate all the fundamental assumptions mad for the design and construction planning of the tower. The Burj Khalifa Project is the tallest structure ever built by man; the tower is 828 meters tall and comprises of 162 floors above grade and 3 basement levels. Early integration of aerodynamic shaping and wind engineering played a major role in the architectural massing and design of this multi-use tower, where mitigating and taming the dynamic wind effects was one of the most important design criteria established at the onset of the project design. Understanding the structural and foundation system behaviors of the tower are the key fundamental drivers for the development and execution of a state-of-the-art survey and structural health monitoring (SHM) programs. Therefore, the focus of this paper is to discuss the execution of the survey and real-time structural health monitoring programs to confirm the structural behavioral response of the tower during construction stage and during its service life; the monitoring programs included 1) monitoring the tower's foundation system, 2) monitoring the foundation settlement, 3) measuring the strains of the tower vertical elements, 4) measuring the wall and column vertical shortening due to elastic, shrinkage and creep effects, 5) measuring the lateral displacement of the tower under its own gravity loads (including asymmetrical effects) resulting from immediate elastic and long term creep effects, 6) measuring the building lateral movements and dynamic characteristic in real time during construction, 7) measuring the building displacements, accelerations, dynamic characteristics, and structural behavior in real time under building permanent conditions, 8) and monitoring the Pinnacle dynamic behavior and fatigue characteristics. This extensive SHM program has resulted in extensive insight into the structural response of the tower, allowed control the construction process, allowed for the evaluation of the structural response in effective and immediate manner and it allowed for immediate correlation between the measured and the predicted behavior. The survey and SHM programs developed for Burj Khalifa will with no doubt pioneer the use of new survey techniques and the execution of new SHM program concepts as part of the fundamental design of building structures. Moreover, this survey and SHM programs will be benchmarked as a model for the development of future generation of SHM programs for all critical and essential facilities, however, but with much improved devices and technologies, which are now being considered by the author for another tall and complex building development, that is presently under construction.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.6B
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• pp.1082-1091
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• 2000

In this paper, the efficient equalization method for OFDM(Orthogonal Frequency Division Multiflexing) System using the QAM(Quadrature Amplitude Modulation) in multipath fading channel is proposed in order to faster and more efficiently equalize the received signals that are sent over real channel. In generally, the one-tap linear equalizers have been used in the frequency-domain as the existing equalization method for OFDM system. In this technique, if characteristics of the channel are changed fast, the one-tap linear equalizers cannot compensate for the distortion due to time variant multipath channels. Therefore, in this paper, we use one-tap non-linear equalizers instead of using one-tap linear equalizers in the frequency-domain, and also use the linear equalizer in the time-domain to compensate the rapid performance reduction at the low SNR(Signal-to-Noise Ratio) that is the disadvantage of the non-linear equalizer. In the frequency-domain, when QAM signals, consisting of in-phase components and quadrature (out-phase) components, are sent over the complex channel, the only in-phase and quadrature components of signals distorted by the multipath fading are changed the same as signals distorted by the noise. So the cross components are canceled in the frequency-domain equalizer. The time-domain equalizer and the adaptive algorithm that has lower-error probability and fast convergence speed are applied to compensate for the error that is caused by canceling the cross components in the frequency-domain equalizer. In the time-domain, To compensate for the performance of frequency-domain equalizer the time-domain equalizes the distorted signals at a frame by using the Gold-code as a training sequence in the receiver after the Gold-codes are inserted into the guard signal in the transmitter. By using the proposed equalization method, we can achieve faster and more efficient equalization method that has the reduced computational complexity and improved performance.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.37-47
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• 2016

The practical constraints on the commercial FPGAs which contain dedicated wide function multiplexers in their slice structure are incorporated with one of the most advanced FPGA mapping algorithms based on the AIG (And-Inverter Graph), one of the best logic representations in academia. As the first step of the mapping process, cuts are enumerated as intermediate structures. And then, the cuts which can be mapped to the multiplexers are recognized. Without any increased complexity, the delay and area of multiplexers as well as LUTs are calculated after checking the requirements for the tree construction such as symmetry and depth limit against dynamically changing mapping of neighboring nodes. Besides, the root positions of multiplexer trees are identified from the RTL code, and annotated to the AIG as AOs (Auxiliary Outputs). A new AIG embedding the multiplexer tree structures which are intentionally synthesized by Shannon expansion at the AOs, is overlapped with the optimized AIG. The lossless synthesis technique which employs FRAIG (Functionally Reduced AIG) is applied to this approach. The proposed approach and techniques are validated by implementing and applying them to two RISC processor examples, which yielded 13~30% area reduction, and up to 32% delay reduction. The research will be extended to take into account the constraints on the dedicated hardware for carry chains.

• The Journal of the Korea Contents Association
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• v.13 no.2
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• pp.19-31
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• 2013

Since the high readable source codes help us to understand and modify the program, it is much easy to maintain them. The readability of source code is not only affected by the complexity of algorithms such as control structures but also affected by the coding styles such as naming and indentation. Although various coding standards have been presented for promoting the readability of source codes, it has been usually lost or ignored in a programming course. One of the reasons is that the coding standard is not a hard-and-false rule since it does not contribute to the performance of software. In this paper, we propose a simple automatic system, namely StyleJigsaw, which checks the style of the source codes written by C/C++ or Java. In this system, the coding style score is calculated and visualized as a jigsaw puzzle. To measure the educational effectiveness of StyleJigsaw, several experiments have been conducted on a class students in C++ programming course. According to the experimental results, the coding style score increased about 8.0 points(10.9%) on average using StyleJigsaw. Further, according to a questionnaire survey targeting the students who attended the programming course, about 88.5% of the students responded that StyleJigsaw was of help to learn the coding standards. We expect that the StyleJigsaw can be effectively used to encourage the students to obey the coding standards, resulting in high readable programs.

• Journal of Convergence Society for SMB
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• v.3 no.2
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• pp.51-56
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• 2013

Real-time processing of sensor data network, is one of the important factors. Each node in the detected data are required to be transmitted within a certain time since the accurate processing is possible. Thus, the data nodes are successfully delivered within a specified time, it is very important to check whether the. Recently more and more accurate real-time embedded systems are reliable and haejyeoseo been able to provide sophisticated services. Because of the inherent complexity of embedded systems in the physical world and the difficulty of predicting the difficulty of a safe design constraints on the runtime violation of system as to cause unexpected causes. Each node data in time detected by the time required to be passed in the appropriate processing is possible because the data transfer time in this paper, the monitoring of the sensor network through a node are allowed to exist within the time range and transmits data to the server Analysis of the data transfer time for checking whether the system was implemented. Implementation of the data transmission time to the process for analyzing and presenting, according to the procedure suggested by the transit time required for analysis a time difference analysis method, a data collection method and a data transmission time and transmission time calculating method presented.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.6A
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• pp.341-350
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• 2003

In this paper, we evaluate the performance of a moving average (MA) channel estimation filter when space-time block coding transmit diversity (STBC-TD) is applied to the wideband direct sequence code division multiple access (WCDMA) forward link. And we present the infinite impulse response (IIR) filter scheme that can reduce the required memory buffer and the channel estimation delay time. This paper also compares the performance between MA filter scheme and IIR filter scheme in various Rayleigh fading channel environments through the bit error rate (BER) and the frame error rate (FER). Extensive computer simulation results show that transmission with STBC-TD provides a significant gain in performance over no transmit diversity technique, particularly at pedestrian speeds. If STBC-TD technique is employed in the channel estimator based on MA filter, it provides considerable performance gains against Rayleigh fading and reduces the optimum filter tap number. Consequently, the channel estimation delay time and the complexity of the receiver are reduced. In addition, the channel estimator based on IIR filter has the advantages such as little memory requirement and no delay time compared to the MA scheme. However, IIR filter coefficients is very sensitive to the mobile speed change and it exerts a serious influence upon the performance. For that reason, it is important to set uP the optimum IIR filter coefficients.

• Journal of the Korea Society of Computer and Information
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• v.25 no.6
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• pp.1-8
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• 2020

Communication between system modules is applied using the Modbus protocol in industrial sites including smart factories, industrial drones, building energy management systems, PLCs, ships, trains, and airplanes. The existing Modbus was used for serial communication, but the recent Modbus protocol is used for TCP/IP communication.The Modbus protocol supports RTU, TCP and ASCII, and implements and uses protocols in embedded systems. However, the transmission I/O devices for RTU, TCP, and ASCII-based protocols may differ. For example, RTU and ASCII communications transmit on a serial-based communication protocol, but in some cases, Ethernet TCP/IP transmission is required. In particular, since the C language (object-oriented) is used in embedded systems, the complexity of source code related to I/O registers increases. In this study, we designed software that can logically separate I/O functions from embedded devices, and designed the execution logic of each instance requiring I/O processing through a delegate class instance with Modbus RTU, TCP, and ASCII protocol generation. We designed and experimented with software that can separate communication I/O processing and logical execution logic for each instance.