• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.5
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• pp.719-725
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• 1986

Reed-solomon(R-S) code is very effective to coerrect both random and burst errors over a noise communication channel. However, the required hardware is very complex if the B/M algorithm was employed. Moreover, when the error correction system consists of two R-S decoder and de-interleave, the I/O data bns lines becomes 9bits because of an erasure flag bit. Thus, it increases the complexity of hardware. This paper describes the R-S decoder which consisits of a error correction section that uses a direct decoding algorithm and erasure generation section and a erasure generation section which does not use the erasure flag bit. It can be shown that the proposed R-S dicoder is very effective in reducing the size of required hardware for error correction.

• Journal of the Korea Society of Computer and Information
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• v.14 no.12
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• pp.225-232
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• 2009

Function Point Method have been applied to measure software size estimation in industry because it supports to estimate the software's size by user's view not developer's. However, the current function point method has some problems for example complexity's upper limit etc. So, In this paper, an enhanced function point model. Micro FP model, was suggested. Using this model, software effort estimation can be more efficiently because this model has some regression equation. This model specially can be applied to estimate in detail the large application system's size Analysis results show that measured software size by this Micro FP model has the advantage with more correlative between the one of LOC, as of 10 applications operated in an large organization.

• Journal of Positioning, Navigation, and Timing
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• v.11 no.1
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• pp.11-21
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• 2022

Fast Fourier transform (FFT)-based parallel acquisition techniques with reduced computational complexity have been widely used for the acquisition of binary phase shift keying (BPSK) global positioning system (GPS) signals. In this paper, we propose a low computational FFT-based fine acquisition technique, for binary offset carrier (BOC) modulated BPSK signals, that depending on the subcarrier-to-code chip rate ratio (SCR) selectively utilizes the computationally efficient frequency-domain realization of the BPSK-like technique and two-dimensional compressed correlator (BOC-TDCC) technique in the first stage in order to achieve a fast coarse acquisition and accomplishes a fine acquisition in the second stage. It is analyzed and demonstrated that the proposed technique requires much smaller mean fine acquisition computation (MFAC) than the conventional FFT-based BOC acquisition techniques. The proposed technique is one of the first techniques that achieves a fast FFT-based fine acquisition of BOC signals with a slight loss of detection probability. Therefore, the proposed technique is beneficial for the receivers to make a quick position fix when there are plenty of strong (i.e., line-of-sight) GNSS satellites to be searched.

• Journal of Korea Multimedia Society
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• v.10 no.11
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• pp.1427-1438
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• 2007

Video watermarking technologies are classified into types of four kinds. The first type is to embed the watermark into a raw video signal and to code the watermarked video signal. Most of video watermarking technologies fall into the category of this type. The second type is to apply watermarking to the coding process, such as block DCT and quantization. The third is to directly embed the watermark into the compressed bitstream itself. Generally, it is referred as labelling rather than watermarking. Finally, the fourth is to embed the water mark into MPEG motion vector. This type has the difficulty in real-time process because of the high complexity and has the blocking effects because of DCT-based on coder. In this paper, we proposed the digital video watermarking that embed the watermark in SPIHT video code for I-frame using motion vector analysis. This method can remove the blocking effect occurred at the DCT-based on coder and obtain video data that has progressive transmission property. The proposed method is to select the region for the watermark embedding in I frame using motion vector estimated from the previous P or B frame. And then, it is to perform DWT and embed the watermark based on HVS into the wavelet coefficients in the same subband of DWT as the motion vector direction. Finally, the watermarked video bitstream is obtained by the SPIHT coder. The experimental results verified that the proposed method has the invisibility from the objective and subjective image quality and the robustness against the various SPIHT compression and MPEG re-code.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.9
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• pp.16-23
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• 2009

In this paper, we propose a new distributed Alamouti space-time block coding scheme using cooperative relay system composed of one source node, three relay nodes and one destination node. The source node is assumed to be equipped with two antennas which respectively use a 2-beam array to communicate with two nodes selected from the three relay nodes. During the first time slot, the two signals which respectively were transmitted by one antenna at the source, are selected by one relay node, added, amplified, and forwarded to the destination. During the second time slot, the other two relay nodes implement the conjugate and minusconjugate operations to the two received signals, respectively, each in turn is amplified and forwarded to the destination node. This transmission scheme represents a new distributed Alamouti space-time block code that can be constructed at the relay-destination channel. Through an equivalent matrix expression of symbols, we analyze the performance of this proposed space-time block code in terms of the chernoff upper bound pairwise error probability (PEP). In addition, we evaluate the effect of the coefficient $\alpha$ ($0{\leq}{\alpha}{\leq}1$) determined by power allocation between the two antennas at the source on the received signal performance. Through computer simulation, we show that the received signals at the three relays have same variance only when the value of $\alpha$ is equal to $\frac{2}{3}$, as a consequence, a better performance is obtained at the destination. These analysis results show that the proposed scheme outperforms conventional proposed schemes in terms of diversity gain, PEP and the complexity of relay nodes.

• Journal of the Korea Convergence Society
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• v.10 no.12
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• pp.53-61
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• 2019

The risk of project failure has increased recently as ERP systems have been transformed into Web environments and task complexity has increased. Although low-code platform development tools are being used as a way to solve this problem, limitations exist as they are centered on UI. To overcome this, back-end development tools are required that can be developed quickly and easily, not only from the front development but also from a variety of development sources produced from the ERP development process, including back-end business services. In addition, the development tools included within existing ERP products require a lot of learning time from the perspective of beginner and intermediate developers due to high entry barriers. To address these shortcomings, this paper seeks to study ways to overcome the limitations of existing development tools within the ERP by providing customized development tool functions by enhancing the usability of ERP development tools suitable for each developer's skills and roles based on the requirements required by ERP development tools, such as reducing the time required for querying, automatic binding of data for testing for service-based units, and checking of source code quality.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.4
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• pp.819-826
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• 2018

The generalized Hamming weight is one of the important parameters of the linear code. It determines the performance of the code when the linear codes are applied to a cryptographic system. In addition, when the block code is decoded by soft decision using the lattice diagram, it becomes a measure for evaluating the state complexity required for the implementation. In particular, a bit-parallel multiplier on finite fields based on trinomials have been studied. Cellular automata(CA) has superior randomness over LFSR due to its ability to update its state simultaneously by local interaction. In this paper, we deal with the efficient synthesis of the pseudo random number generator, which is one of the important factors in the design of effective cryptosystem. We analyze the property of the characteristic polynomial of the simple 90/150 transition rule block, and propose a synthesis algorithm of the reversible 90/150 CA corresponding to the trinomials $x^2^n+x^{2^n-1}+1$($n{\geq}2$) and the 90/150 reversible CA(RCA) corresponding to the maximum weight polynomial with $2^n$ degree by using this rule block.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.24 no.5
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• pp.871-883
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• 2014

New types of attacks that mainly compromise the public, portal and financial websites for the purpose of economic profit or national confusion are being emerged and evolved. In addition, in case of 'drive by download' attack, if a host just visits the compromised websites, then the host is infected by a malware. Website falsification detection system is one of the most powerful solutions to cope with such cyber threats that try to attack the websites. Many domestic CERTs including NCSC (National Cyber Security Center) that carry out security monitoring and response service deploy it into the target organizations. However, the existing techniques for the website falsification detection system have practical problems in that their time complexity is high and the detection accuracy is not high. In this paper, we propose website falsification detection system based on image and code analysis for improving the performance of the security monitoring and response service in CERTs. The proposed system focuses on improvement of the accuracy as well as the rapidity in detecting falsification of the target websites.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39A no.12
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• pp.708-717
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• 2014

In this paper, we present a secret key distribution protocol without resorting to a key management infrastructure targeting at providing a low-complexity distributed solution to wireless network. The proposed scheme extracts a secret key from the random fluctuation of wireless channels. By exploiting time division duplexing transmission, two legitimate users, Alice and Bob can have highly correlated channel gains due to channel reciprocity, and a pair of random bit sequences can be generated by quantizing the channel gains. We propose a novel adaptive quantization scheme that adjusts quantization thresholds according to channel variations and reduces the mismatch probability between generated bit sequences by Alice and Bob. BCH codes, as a low-complexity and pratical approach, are also employed to correct the mismatches between the pair of bit sequences and produce a secret key shared by Alice and Bob. To maximize the secret key extraction rate, the parameters, quantization levels and code rates of BCH codes are jointly optimized.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.3
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• pp.699-707
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• 2016

This paper proposes a low-complexity central processing unit (CPU) that is suitable for deeply embedded systems, including Internet of things (IoT) applications. The core features a 16-bit instruction set architecture (ISA) that leads to high code density, as well as a multicycle architecture with a counter-based control unit and adder sharing that lead to a small hardware area. A co-processor, instruction cache, AMBA bus, internal SRAM, external memory, on-chip debugger (OCD), and peripheral I/Os are placed around the core to make a system-on-a-chip (SoC) platform. This platform is based on a modified Harvard architecture to facilitate memory access by reducing the number of access clock cycles. The SoC platform and CPU were simulated and verified at the C and the assembly levels, and FPGA prototyping with integrated logic analysis was carried out. The CPU was synthesized at the ASIC front-end gate netlist level using a $0.18{\mu}m$ digital CMOS technology with 1.8V supply, resulting in a gate count of merely 7700 at a 50MHz clock speed. The SoC platform was embedded in an FPGA on a miniature board and applied to deeply embedded IoT applications.