• Journal of the Institute of Convergence Signal Processing
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• v.6 no.2
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• pp.95-99
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• 2005

This paper presents an accurate recovery method of the reference clock which is needed for network synchronization in two-way satellite multimedia systems compliant with DVB-RCS specification and which use closed loop method for burst synchronization. In these systems, the remote station transmits TDMA burst via return link. For burst synchronization, it obtains reference clock from program clock reference (PCR) defined by MPEG-2 system specification. The PCR is generated periodically at the hub system by sampling system clock which runs at 27MHz $\pm$ 30ppm. Since the reference clock is recovered by means of digital PLL(DPLL) using imprecise PCR values due to variable random jitter, the recovered clock frequency of remote station doesn't exactly match reference clock of hub station. We propose a robust recovery method of reference clock against random delay jitter The simulation results show that the recovery error is remarkably decreased from 5 clocks to 1 clock of 27MHz relative to the general DPLL recovery method.

• Journal of Positioning, Navigation, and Timing
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• v.8 no.4
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• pp.209-214
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• 2019

Precise point positioning (PPP) requires precise orbit and clock products. International GNSS service (IGS) real-time service (RTS) data can be used in real-time for PPP, but it may not be possible to receive these corrections for a short time due to internet or hardware failure. In addition, the time required for IGS to combine RTS data from each analysis center results in a delay of about 30 seconds for the RTS data. Short-term orbit prediction can be possible because it includes the rate of correction, but the clock correction only provides bias. Thus, a short-term prediction model is needed to preidict RTS clock corrections. In this paper, we used a long short-term memory (LSTM) network to predict RTS clock correction for three minutes. The prediction accuracy of the LSTM was compared with that of the polynomial model. After applying the predicted clock corrections to the broadcast ephemeris, we performed PPP and analyzed the positioning accuracy. The LSTM network predicted the clock correction within 2 cm error, and the PPP accuracy is almost the same as received RTS data.

• Journal of the Korea Society of Computer and Information
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• v.13 no.1
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• pp.175-183
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• 2008

QoS-support technology in networks is based on measuring QoS metrics which reflect a magnitude of stability and performance. The one-way delay measurement of the QoS metrics especially requires a guarantee of clock synchronization between end-to-end hosts. However, the hosts in networks have a relative or absolute difference in clock time by reason of clock offsets. flock skews and clock adjustments. In this paper, we present a theorem, methods and simulation results of one-way delay and clock offset estimations between end-to-end hosts. The proposed theorem is a relationship between one-way delay, one-way delay variation and round-trip time And we show that the estimation error is mathematically smaller than a quarter of round-trip time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.23-30
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• 2005

This paper describes a DLL(delay locked loop)-based multi-clock generator having the lower active stand-by power as well as a fast relocking after re-activating the DLL. for low power and high speed VLSI chip. It enables a frequency multiplication using frequency multiplier scheme and produces output clocks with 50:50 duty-ratio regardless of the duty-ratio of system clock. Also, digital control scheme using DAC enables a fast relocking operation after exiting a standby-mode of the clock system which was obtained by storing analog locking information as digital codes in a register block. Also, for a clock multiplication, it has a feed-forward duty correction scheme using multiphase and phase mixing corrects a duty-error of system clock without requiring additional time. In this paper, the proposed DLL-based multi-clock generator can provides a synchronous clock to an external clock for I/O data communications and multiple clocks of slow and high speed operations for various IPs. The proposed DLL-based multi-clock generator was designed by the area of $1796{\mu}m\times654{\mu}m$ using $0.35-{\mu}m$ CMOS process and has $75MHz\~550MHz$ lock-range and maximum multiplication frequency of 800 MHz below 20psec static skew at 2.3v supply voltage.

• Journal of IKEEE
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• v.23 no.3
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• pp.858-864
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• 2019

A clock system is proposed to eliminate data loss due to frequency difference between sensor nodes in a sensor utility network. The proposed clock system for each sensor node consists of a bust clock-data recovery (CDR) circuit, a digital phase-locked loop outputting a 32-phase clock, and a digital frequency synthesizer using a programmable open-loop fractional divider. A CMOS oscillator using an active inductor is used instead of a burst CDR circuit for the first sensor node. The proposed clock system is designed by using a 65 nm CMOS process with a 1.2 V supply voltage. When the frequency error between the sensor nodes is 1%, the proposed burst CDR has a time jitter of only 4.95 ns with a frequency multiplied by 64 for a data rate of 5 Mbps as the reference clock. Furthermore, the frequency change of the designed digital frequency synthesizer is performed within one period of the output clock in the frequency range of 100 kHz to 320 MHz.

• Journal of the Korea Society for Simulation
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• v.4 no.2
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• pp.31-40
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• 1995

A hybrid simulation model consists of real physical entities as well as simulated ones. It also contains logical processes for decision making for each operation units, a group of the entities. During the execution of such simulations, the physical and the logical processes consume real clock time while the activity durations of the simulated ones are generated. Due to the inherent chracteristics of the subjects of the communication channels. Since one can not undo an real event already taken place, the traditional central clock approach is used for the synchronization of the events(Kim[6]). However, there are still chances of causality errors due to the randomness in the communication delays. This error is not found in the distributed pure simulations. This paper explains the error in details and proposes a prevention scheme that is simple to implement.

• Journal of the Semiconductor & Display Technology
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• v.22 no.1
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• pp.43-48
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• 2023

This paper discusses the design of 32Mbyte asynchronous nonvolatile memory modules, which includes self-diagnosis and RTC (Real Time Clock) functions to enhance their data stability and reliability. Nonvolatile memory modules can maintain data even in a power-off state, thereby improving the stability and reliability of a system or device. However, due to the possibility of data error due to electrical or physical reasons, additional data loss prevention methods are required. To minimize data error in asynchronous nonvolatile memory modules, this paper proposes the use of voltage monitoring circuits, self-diagnosis, BBT (Bad Block Table), ECC (Error Correction Code), CRC (Cyclic Redundancy Check)32, and data check sum, data recording method using RTC. Prototypes have been produced to confirm correct operation and suggest the possibility of commercialization.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.3
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• pp.577-582
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• 2016

The synchronous TDC(Time-to-Digital Converter) of counter-type using current-conveyor is designed by $0.18{\mu}m$ CMOS process and the supply voltage is 3 volts. In order to compensate the disadvantage of a asynchronous TDC the clock is generated when the start signal is applied and the clock is synchronized with the start signal. In the asynchronous TDC the error range of digital output is from $-T_{CK}$ to $T_{CK}$. But the error range of digital output is from 0 to $T_{CK}$ in the synchronous TDC. The error range of output is reduced by the synchronization between the start signal and the clock when the timing-interval signal is converted to digital value. Also the structure of the synchronous TDC is simple because there is no the high frequency external clock. The operation of designed TDC is confirmed by the HSPICE simulation.

• Journal of the Korea Society of Computer and Information
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• v.18 no.7
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• pp.47-55
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• 2013

Most of the applications implemented in embedded systems use timers equipped in MCU. The purposes of timer usage of the applications lie in a wide range of areas such as implementing software timers of real-time operating systems to measuring processing time of sensors. The elapsed times measured by the applications are various in length as well as in precision ranging from several us to several hundreds of ms. The paper analyzes the timing error factors caused by un- synchronizing timer clock pulse when timers are manipulated, and proposes a method of how to synchronize timer clock pulse to reduce the timing errors. As a result of an experiment, this paper shows that an error of 230us is reduced within 10us in case of appling the proposed method to a 4096Hz timer prescaled from 32768Hz by 8.

• Journal of Advanced Navigation Technology
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• v.26 no.6
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• pp.404-411
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• 2022

The main function in operating the satellite navigation system is to accurately determine the orbit of the navigation satellite and transmit it as a navigation message. In this study, we developed software to determine the orbit of a navigation satellite by combining an extended Kalman filter and an accurate dynamic model. Global positioning system (GPS) and quasi-zenith satellite system (QZSS) orbit determination was performed using international gnss system (IGS) ground station observations and user range error (URE), a key performance indicator of the navigation system, was calculated by comparison with IGS precise ephemeris. When estimating the clock error mounted on the navigation satellite, the radial orbital error and the clock error have a high inverse correlation, which cancel each other out, and the standard deviations of the URE of GPS and QZSS are small namely 1.99 m and 3.47 m, respectively. Instead of estimating the clock error of the navigation satellite, the orbit was determined by replacing the clock error of the navigation message with a modeled value, and the regional correlation with URE and the effect of the ground station arrangement were analyzed.