• Title/Summary/Keyword: clock component

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Development of Closed Caption Decoder System on Broadcast Monitor (방송용 모니터의 방송 자막 디코더 시스템 개발)

  • Song, Young-Kyu;Jeong, Jae-Seok
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 2010.07a
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    • pp.36-39
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    • 2010
  • 멀티 포맷 방송용 모니터는 SDI 신호뿐만 아니라 HDMI, DVI, Component, Composite로 전송되는 영상, 음성, 부가 데이터를 보여주는 모니터로 방송용 레퍼런스 모니터로 사용되고 있다. 특히 부가 데이터 중에서 Closed Caption의 경우 북미에서는 EIA-608과 EIA-708 두 가지 표준이 있고, 세부적으로 네 가지의 방법으로 전송되는데 일반적인 방송용 모니터에는 적용되어 있는 것이 극히 드물다. 또한 SDI 신호로 전송되는 Closed Caption 데이터를 Decoding하는 상용 IC는 거의 없는 수준이다. 이에 본 논문에서는 SDI로 전송되는 다양한 방식의 Closed Caption 데이터를 모두 표시하기 위한 방법을 제안하였다. 먼저 VBI (Vertical Blanking Interval) 에 아날로그 Waveform 형태로 입력되는 경우 데이터의 신뢰도를 높이기 위해 Clock Run In을 실시간으로 검출 할 수 있는 구조를 제안하고 FPGA (Field Programmable Gata Array)로 구현하였다. 또한 VANC (Vertical Ancillary Space)로 들어오는 Caption데이터의 경우 특히 EIA-708 처럼 많은 데이터가 입력되는 경우 실시간으로 처리하기 위해서 기존의 I2C와 같은 느린 전송 방법이 아닌 FPGA와 프로세서 간에 메모리를 직접 Access 할 수 있는 방법을 제안하였다. 본 논문에서 제안 한 방법을 FPGA로 구현하였고, 실제 미국이나 캐나다 방송국에서 사용하는 Caption 인코더 장비 뿐만아니라 방송 콘텐츠를 직접 이용하여 동작 상태를 검증하였다.

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Implementation of CAVLC Encoder for the Image Compression in H.264/AVC (H.264/AVC용 영상압축을 위한 CAVLC 인코더 구현)

  • Jung Duck Young;Choi Dug Young;Jo Chang-Seok;Sonh Seung Il
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.9 no.7
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    • pp.1485-1490
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    • 2005
  • Variable length code is an integral component of many international standards on image and video compression currently. Context-based Adaptive Variable Length Coding(CAVLC) is adopted by the emerging JVT(also called H.264, and AVC in MPEG-4). In this paper, we design an architecture for CAVLC encoder, including a coeff_token encoder, level encoder, total_zeros encoder and run_before encoder. The designed CAVLC encoder can encode one syntax element in one clock cycle. As a result of implementation by Vertex-1000e of Xilinx, its operation frequency is 68MHz. Therefore, it is very suitable for video applications that require high throughput.

Genetic Analysis of absR, a new abs locus of Streptomyces coelicolor

  • Park, Uhn-Mee;Suh, Joo-Won;Hong, Soon-Kwang
    • Journal of Microbiology and Biotechnology
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    • v.10 no.2
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    • pp.169-175
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    • 2000
  • The filamentous soil bacterium Streptomyces coelicolor is known to produce four distinct antibiotics. The simultaneous global regulation for the biosynthesis of those four antibiotics was previously confirmed by absA and absB mutations that blocked all four antibiotics' biosynthesis without influencing their morphological differentiation. To study the complex regulatory cascade that controls the secondary metabolism in Streptomyces, a new abs-like mutation was characterized. namely absR, which is slightly leaky on a complete R2YE medium, yet tight on a minimal medium. A genetic analysis of the absR locus indicated that it is located at 10 o'clock on the genetic map, near the site of absA. A cloned copy of the absA gene that encoded bacterial two-component regulatory kinases did not restore antibiotic biosyntheis to the absR mutant. Accordingly, it is proposed that absR is another abs-type mutation which is less tight than the previously identified absA or absB mutations income medium conditions, and can be used to characterize another global regulatory gene for secondary metabolete formation in S. coelicolor.

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Family of the Sun-and-Stars Time-Determining Instruments (Ilseong-jeongsi-ui) Invented During the Joseon Dynasty

  • Lee, Yong Sam;Kim, Sang Hyuk;Mihn, Byeong-Hee
    • Journal of Astronomy and Space Sciences
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    • v.33 no.3
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    • pp.237-246
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    • 2016
  • We analyze the design and specifications of the Sun-and-Stars Time-Determining group of instruments (Ilseong-jeongsi-ui, 日星定時儀) made during the Joseon dynasty. According to the records of the Sejong Sillok (Veritable Records of King Sejong), Sun-and-Stars Time-Determining Instruments measure the solar time of day and the sidereal time of night through three rings and an alidade. One such instrument, the Simplified Time-Determining Instrument (So-jeongsi-ui, 小定時儀), is made without the essential component for alignment with the celestial north pole. Among this group of instruments, only two bronze Hundred-Interval-Ring Sundials (Baekgak-hwan-Ilgu, 百刻環日晷) currently exist. A comparison of the functions of these two relics with two Time-Determining Instruments suggests that the Hundred-Interval-Ring Sundial is a Simplified Sundial (So-ilyeong, 小日影), as recorded in the Sejong Sillok and the Seongjong Sillok (Veritable Records of King Seongjong). Furthermore, the Simplified Sundial is a model derived from the Simplified Time-Determining Instrument. During the King Sejong reign, the Sun-and-Stars Time-Determining Instruments were used in military camps of the kingdom's frontiers, in royal ancestral rituals, and in royal astronomical observatories.

A Low Power UHF RFID Baseband Processor for Mobile Readers (모바일용 저전력 UHF RFID 기저대역 프로세서)

  • Bae, Sung Woo;Park, Jun-Seok;Seong, Yeong Rak;Oh, Ha-Ryoung
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.63 no.1
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    • pp.85-91
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    • 2014
  • As RFID is utilized more frequently and diversely in terms of its application areas, the application of mobile RFID technology, which integrates cellular networks and RFID, is highly anticipated. The growth and development of the RFID field has bolstered the development of mobile RFID chips to be embedded in mobile phones. Because mobile RFID chips are embedded in cell phones, limitations such as low power, small form factor, and costliness must be confronted. This study presents the design of a RFID digital baseband processor that is suitable for mobile readers. The RF analog component, which affects the baseband signals, is designed separately, in consideration of the limitations stated above. The function of the baseband processor was verified through simulations and prototyped using FPGA. The power consumption of the chip is 20mW under a 20MHz clock and the chip measures $3mm{\times}3mm$.

Architecture Design for Maritime Centimeter-Level GNSS Augmentation Service and Initial Experimental Results on Testbed Network

  • Kim, Gimin;Jeon, TaeHyeong;Song, Jaeyoung;Park, Sul Gee;Park, Sang Hyun
    • Journal of Positioning, Navigation, and Timing
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    • v.11 no.4
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    • pp.269-277
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    • 2022
  • In this paper, we overview the system development status of the national maritime precise point positioning-real-time kinematic (PPP-RTK) service in Korea, also known as the Precise POsitioning and INTegrity monitoring (POINT) system. The development of the POINT service began in 2020, and the open service is scheduled to start in 2025. The architecture of the POINT system is composed of three provider-side facilities-a reference station, monitoring station, and central control station-and one user-side receiver platform. Here, we propose the detailed functionality of each component considering unidirectional broadcasting of augmentation data. To meet the centimeter-level user positioning accuracy in maritime coverage, new reference stations were installed. Each reference station operates with a dual receiver and dual antenna to reduce the risk of malfunctioning, which can deteriorate the availability of the POINT service. The initial experimental results of a testbed from corrections generated from the testbed network, including newly installed reference stations, are presented. The results show that the horizontal and vertical accuracies satisfy 2.63 cm and 5.77 cm, respectively. For the purpose of (near) real-time broadcasting of POINT correction data, we designed a correction message format including satellite orbit, satellite clock, satellite signal bias, ionospheric delay, tropospheric delay, and coordinate transformation parameters. The (near) real-time experimental setup utilizing (near) real-time processing of testbed network data and the designed message format are proposed for future testing and verification of the system.

Area Efficient FPGA Implementation of Block Cipher Algorithm SEED (블록 암호알고리즘 SEED의 면적 효율성을 고려한 FPGA 구현)

  • Kim, Jong-Hyeon;Seo, Young-Ho;Kim, Dong-Wook
    • Journal of KIISE:Computing Practices and Letters
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    • v.7 no.4
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    • pp.372-381
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    • 2001
  • In this paper SEED, the Korea Standard 128-bit block cipher algorithm is implemented with VHDL and mapped into one FPGA. SEED consists of round key generation block, F function block, G function block, round processing block, control block and I/O block. The designed SEED is realized in an FPGA but we design it technology-independently so that ASIC or core-based implementation is possible. SEED requires many hardware resources which may be impossible to realize in one FPGA. So it is necessary to minimize hardware resources. In this paper only one G function is implemented and is used for both the F function block and the round key block. That is, by using one G function sequentially, we can realize all the SEED components in one FPGA. The used cell rate after synthesis is 80% in Altem FLEXI0KlOO. The resulted design has 28Mhz clock speed and 14.9Mbps performance. The SEED hardware is technology-independent and no other external component is needed. Thus, it can be applied to other SEED implementations and cipher systems which use SEED.

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The Influence of Circadian Gene Per2 on Cell Damaged by Ultraviolet C

  • Liu, Yanyou;Wang, Yuhui;Jiang, Zhou;Xiao, Jing;Wang, Zhengrong
    • Biomolecules & Therapeutics
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    • v.19 no.3
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    • pp.308-314
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    • 2011
  • It has been shown that circadian genes not only play an important role on circadian rhythms, but also participate in other physiological and pathological activities, such as drug dependence, cancer development and radiation injury. The Per2, an indispensable component of the circadian clock, not only modulates circadian oscillations, but also regulates organic function. In the present study, we applied mPER2-upregulated NIH3T3 cells to reveal the relationship of mPer2 and the cells damaged by ultraviolet C (UVC). NIH3T3 cells at the peak of the expression of mPer2 induced by phorbol 12-myristate 13-acetate (PMA) demonstrated little damage by UVC evaluated by MTT assay, cell growth curves and cell colony-forming assay, compared with that at the nadir of the expression of mPer2. Overexpression of mPER2, accompanied p53 upregulated, also demonstrated protective effect on NIH3T3 cells damaged by UVC. These results suggest that mPer2 plays a protective effect on cells damaged by UVC, whose mechanism may be involved in upregulated p53.

Design of Measuring Trays in the Irrigation System Using Drainage Electrodes for Tomato Perlite Bed Culture (토마토 펄라이트 베드재배시 배액전극 제어법에 적합한 측정틀 설계)

  • Kim, Sung-Eun;Kim, Young-Shik;Sim, Sang-Youn
    • Horticultural Science & Technology
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    • v.29 no.6
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    • pp.568-574
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    • 2011
  • Measuring tray as a component in irrigation control system using drainage electrodes was designed and applied for tomato perlite bed culture, and the effectiveness of the irrigation control system was investigated in terms of cultural development and cultivation costs. Five different types of measuring trays equipped with drainage electrodes were tested and the traditional tray was used as the control equipped with time clock. After the first experiment, "Tube-2" was removed because of instability of water content in the substrate. After second experiment, "Tube-1" was removed because of instability of water content in the substrate and low plant yields. In third experiment, "Up-Board" exhibited the best stability in water contents and yields as well as efficiencies in water and fertilizer utilization. The "Up-Board" was the most economical and the easiest system among the tested trays. Therefore, the "Up-Board" system was concluded as the excellent design to apply for the control method using drainage electrodes for tomato perlite bed culture.

A Full Digital Multipath Generator (완전 디지털 다중경로발생기)

  • 권성재
    • Journal of Korea Society of Industrial Information Systems
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    • v.7 no.2
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    • pp.74-81
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    • 2002
  • In general, a multipath generator consists of a time delay generator, phase rotator, and amplitude attenuator, and is implemented mostly in an analog manner. Analog, or partially analog versions of a multipath generator is disadvantageous in that they may suffer from problems associated with component aging and adjustment, signal fidelity degradation stemming from repeated A/D and D/A conversion use of high frequency to achieve fine i.e., subsample fractional tin delays. This paper presents the design and implementation methodology of a full digital multipath generator which can be used in performance evaluations of digital terrestrial television as well as communications, receivers. In particular, an efficient practical method is proposed which can achieve both integer and fractional time delays simultaneously, without placing restrictions on the allowable system master clock frequency. The proposed algorithm lends itself to minimizing hardware implementation cost by relegating some fixed put of the computation involved to an IBM PC. The proposed multipath generator occupies only a single digital board space, and its experimental results are provided to corroborate the proposed implementation methodology.

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