• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.33 no.2
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• pp.151-154
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• 2020

Radiation noise due to EMI noise generated by the driving circuits of LED lighting devices in a medical imaging room was reduced by decreasing the noise source in the driving circuits and changing the number of corrections in EMI filters. Noise attenuation and filter changes enabled driving circuits that reduced the electromagnetic waves. Such circuits were efficiently designed by using capacitors and inverters in a given space. Therefore, the malfunction of radiation devices can be minimized by using EMI-reduction filter circuits, and reliable operation of medical devices can be expected by blocking electromagnetic waves.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2002.10a
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• pp.750-753
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• 2002

At present, almost circuits are wired using copper in flexible circuits. But, these circuit have limit to flexibility so it occurs fracture about cyclic bending and, thermal load of bending stress occur a circuit trouble. a study of all-polymer flexible circuits get over that problem. Established fabrication method of all-polymer circuits is photolithograph. This method can not have mass production, so this method wastes time and human effort. In this study, all polymer flexible circuits are fabricated using the inkjet process.

• Journal of Sensor Science and Technology
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• v.23 no.2
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• pp.73-81
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• 2014

Silicon PIN diode radiation sensors and CMOS readout circuits were designed and fabricated in this study. The PIN diodes were fabricated using a 380-${\mu}m$-thick 4-inch n+ Si (111) wafer containing a $2-k{\Omega}{\cdot}cm$ n- thin epitaxial layer. CMOS readout circuits employed the driving and signal processes in a radiation sensor were mixed with digital logic and analog input circuits. The primary functions of readout circuits are amplification of sensor signals and the generation of the alarm signals when radiation events occur. The radiation sensors and CMOS readout circuits were fabricated in the Institute of Semiconductor Fusion Technology (ISFT) semiconductor fabrication facilities located in Kyungpook National University. The performance of the readout circuit combined with the Si PIN diode sensor was demonstrated.

• Journal of the Semiconductor & Display Technology
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• v.19 no.3
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• pp.68-72
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• 2020

A new method for array testing of TFT-CD panel with the integrated gate driver circuits is presented. As larger size/high resolution TFT-LCD with the peripheral driver circuits has emerged, one of the important problems for manufacturing is array testing on the panel. This paper describes the technology of detecting defective arrays and optimizing the array testing process. For the effective characterization of pixel array, the pixel storage capability is simulated and measured with voltage imaging system. This technology permits full functional testing during the manufacturing process, enabling fabrication of large TFT-LCD panels with the integrated driver circuits.

• Proceedings of the KIEE Conference
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• 1994.07b
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• pp.1286-1288
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• 1994

Methods are described for the design and fabrication of the sensor circuits on the polarographic oxygen sensing electrodes. The discussion includes: a method for the +5V single-supply driving for the sensor circuits, a method of low power comsumption for the front-end electronics. Typical polarograms for the commercial DO probes using this sensor circuits are presented. High accuracy of the I to V conversion using the circuits is verified.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.7
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• pp.1118-1127
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• 1990

In this paper a new test generation method for Domino CMOS logic circuits is proposed. Because the stuck-at type fault is not adequate for Domino CMOS circuits the stuck-open fault, stuck-on fault and bridging fault are considered as fault models. It is shown that the test generation problem of Domino CMOS circuits results in functional block test generation problem. Test set is generated by using the logic minimizer which is a part of logic design system. An algorithm for reduction of test set is described. The proposed test method can be easily applied to various figures of circuits and make it easy to construct automatic test generator in design system. The proposed algorithms are programed and their efficiency is confirmed by examples.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.383-386
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• 2000

There are some variations in quiescent supply current or TTL SSIs. Thus, some variations in quiescent supply current of logic circuits made of TTL SSIs will be generated. The variations make it difficult to apply supply current test methods to tests of TTL circuits. In this paper, in order to examine the applicability to R circuits, fault coverages of a supply current test method for open faults in some ISCAS-85 benchmark circuits are evaluated, Which are made of TTL LS-type SSIs. The experimental results shows that if SSIs are used for implementation having the variation of quiescent supply current within 1%, supply current test methods are applicable for the tests.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.1017-1020
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• 2000

In this paper, a CNN using 1-dimensional chaos circuits with controllable nonlinear functions is proposed. The proposed CNN consists of $\p{times}q$ chaos circuits which are called cell circuits. The nonlinear functions of the cell circuits can be controlled by employing fuzzy scheme. Thanks to the controllability of the nonlinear functions, the proposed circuit can adjust transition behavior of the CNN electronically. Furthermore, the chaotic behavior of the cell circuit which is a portion of the proposed CNN is simple since the cell circuit is a 1-dimensional chaos circuit. To confirm the validity of the circuit design, SPICE simulations were performed concerning the proposed CNN.

• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.3
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• pp.181-190
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• 2019

Active power decoupling circuits have emerged to eliminate the inherent second-order ripple power in a single-phase power conversion system. This study proposes a design method to determine the optimal capacitance for active power decoupling circuits to achieve high power density. Minimum capacitance is derived by analyzing ripple power in a passive power decoupling circuit, a buck-type circuit, and a capacitor-split-type circuit. Double-frequency ripple power decoupling capabilities are also analyzed in three decoupling circuits under a 3.3 kW load condition for a battery charger application. To verify the proposed design method, the performance of the three decoupling circuits with the derived minimum capacitance is compared and analyzed through the results of MATLAB -Simulink and hardware-in-the-loop simulations.

• Progress in Superconductivity
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• v.3 no.1
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• pp.17-22
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• 2001

Practical implementation of the SFQ technology in most application requires more than single-chip-level circuit complexity. Multiple chips have to be integrated with a technology that is reliable at cryogenic temperatures and supports an inter-chip data transmission speed of tens of GHz. In this work, we have studied two basic issues in building large RSFQ circuits. The first is the reliable inter-chip SFQ pulse transfer technique using Multi-Chip-Module (MCM) technology. By noting that the energy contained in an SFQ pulse is less than an attojoule, it is not very surprising that the direct transmission of a single SFQ pulse through MCM solder bump connectors can be difficult and an innovative technique is needed. The second is the recycling of the bias currents. Since RSFQ circuits are dc current biased the large RSFQ circuits need serial biasing to reduce the total amount of current input to the circuit.