• Bulletin of the Korean Mathematical Society
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• v.52 no.6
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• pp.2047-2069
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• 2015

The coset diagrams are composed of fragments, and the fragments are further composed of circuits at a certain common point. A condition for the existence of a certain fragment ${\gamma}$ of a coset diagram in a coset diagram is a polynomial f in ${\mathbb{Z}}$[z]. In this paper, we answer the question: how many polynomials are obtained from the fragments, evolved by joining the circuits (n, n) and (m, m), where n < m, at all points.

• Journal of Information Display
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• v.5 no.4
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• pp.1-6
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• 2004

In this paper, we investigate on the characteristics of poly-Si TFTs reuired for the implementation of analog circuits to be integrated with System-on-Glass (SoG). Matching requirements in terms of resistor values, threshold voltage and mobility of poly-Si TFTs are derived as a function of the resolution of display system. Effective mobility of poly-Si TFTs required for the realization of source driver is analyzed for various panel sizes.

• 전기의세계
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• v.23 no.6
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• pp.18-19
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• 1974

회로이론의 분야는 꾸준히 성장하여 왔고 System modeling과 system analysis가 새로운 분야로서 등장되어 IEEE에서도 1972. 9. 18. Circuits group를 circuits & Systems Society로 개칭하게 되었다. 회로이론과 그 기교는 비단 전기 및 전자공학에만 적용되는것이 아니라 대시스템분야, 생의학분야, 경제분야에도 공히 적용될 수 있다. 본고에서는 회로 및 시스템분야에 있었던 주요 연구경향을 1974 IEEE International Symposium on Circuits and System에 근거를 두고 미국중심으로 살펴보고 국내 전기 및 전자공학회지를 추적하여 최근의 국내 및 국외 연구동향에 대하여 알아보고자 한다.

• Electrical & Electronic Materials
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• v.11 no.11
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• pp.53-65
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• 1998

Planar lightwave circuits (PLCs) provide various important devices for optical wavelength division multiplexing (WDM) systems, subscriber networks and etc. This paper reviews the recent progress and future prospects of PLC technologies including arrayed-waveguide grating multiplexers, optical add/drop multiplexers, programmable dispersion equalizers and hybrid optoelectronics integration technologies.

• Journal of the Semiconductor & Display Technology
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• v.2 no.4
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• pp.1-7
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• 2003

In this paper, we design the pattern generator circuits using PLDs(Programmable Logic Devices). The pattern generator is the circuit which generates the test pattern signal for the inspection of logical defects of semiconductor products. The proposed circuits are designed by the PLD design tool(MAX+ II of ALTERA). Also the designed circuits are simulated for the verification of the designed ones. The simulation results have a good performance.

• ETRI Journal
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• v.23 no.3
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• pp.138-149
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• 2001

Due to the rapidly growing complexity of VLSI circuits, test methodologies based on delay testing become popular. However, most approaches cannot handle custom logic blocks which are described by logic functions rather than by circuit primitive elements. To overcome this problem, a new path delay test generation algorithm is developed for custom designs. The results using benchmark circuits and real designs prove the efficiency of the new algorithm. The new test generation algorithm can be applied to designs employing intellectual property (IP) circuits whose implementation details are either unknown or unavailable.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.5
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• pp.387-397
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• 1991

This paper presents the design and implementation of a performance-driven logic synthesis system that automatically generates circuits satisfying the given timing and fanout constraints in minimal silicon area. After performing technology independent and dependent optimization, the system identifies and resynthesizes the gates with large loading delay due to excessive fanouts to eliminate the critical path. Experimental results for MCNC benchmark circuits show that proposed system generates the circuits with less delay by up to 20%.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1622-1625
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• 2002

This paper studies the bifurcation of combinatorial oscillations in coupled Duffing’s circuits when symmetry is broken. The system consists of two periodic farced circuits coupled by a linear resistor, These two periodic external forces are sinusoidal voltage sources with various phase-shift. We investigate the relation between phase-shift and periodic solutions by analyzing many bifurcation diagrams.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.579-582
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• 2000

In this paper, new linearization technique for bipolar OTAs using exponential-law circuits is described. The core circuit of the proposed OTAs is the multi-TANH doublet. The OTAs have adaptively biasing current sources, which consists of the exponential-law circuits. Three types of the OTAs are presented. The linear input voltage ranges of the OTAs are almost the same as the multi-TANH triplet. Further, the OTAs have lower power dissipation than the multi-TANH triplet.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.29B no.9
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• pp.1-7
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• 1992

This paper proposes a built-in self-test tchnique for CMOS circuits. To detect a stuck-open fault in CMOS circuits, two consequent test patterns is required. The ordered pairs of test patterns for stuck-open faults are generated by feedback shift registers of extended length. A nonlinear feedback shift register is designed by the merging method and reordering algorithms of test patterns proposed in this paper. And a new multifunctional BILBO (Built-In Logic Block Observer) is designed to perform both test pattern generation and signature analysis efficiently.