• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.4
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• pp.255-261
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• 2005

With the advent of sub-90nm technologies, the system-on-chip (SoC) and system-in-package (SiP) are becoming the trend in delivering low-cost, low-power, and small-form-factor consumer electronic systems running at multiple GHz. The shortened transistor channel length reduces the transistor switching cycles to the range of several picoseconds, yet the time-of-flights of the critical on-chip and off-chip interconnects are in the range of 10 picoseconds for 1.5mm-long wires and 100 picoseconds for 15mm-long wires. Designers realize the bottleneck today often lies at chip-to-chip interconnects and the industry needs a good model to compute the inductance in these parts of circuits. In this paper we propose a new method for extracting accurate equivalent inductance circuit models for SPICE-level circuit simulations of system-on-chip (SoC) and system-in-package (SiP) designs. In our method, geometrical meshes are created and numerical methods are used to find the solutions for the electromagnetic fields over the fine meshes. In this way, multiple-GHz SoC and SiP designers can use accurate inductance modeling and interconnect optimization to achieve high yields.

• The Transactions of the Korean Institute of Power Electronics
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• v.13 no.1
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• pp.1-8
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• 2008

A dynamic model for II-SEPIC(Isolated Inverse-SEPIC) is developed based on the state-space averaging method and its control characteristics are investigated in this paper. Equations for circuit design of II-SEPIC are derived through steady state analysis and the resulted circuit parameters are used in the consequent simulation and experiment works. A structure of control system is devised to obtain better control performance. In order to verify validity and effectiveness of the design equations and dynamic model derived, dynamic control responses of II-SEPIC system against line and load variation are illustrated in both simulation and experiment.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.10
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• pp.1910-1915
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• 2007

An accurate and simple method to extract equivalent circuit parameters of fully-depleted silicon-on-insulator MOSFETs small-signal modeling operating at RF frequencies including the non-quasi static effects is presented in this article. The advantage of this method is that a unique and physically meaningful set of intrinsic equivalent circuit parameters is extracted by de-embedding procedure of extrinsic elements such as parasitic capacitances and resistances of MOSFETs from measured S-parameters using simple Z- and Y- matrices calculations. The calculated small-signal parameters using the presented extraction method give modeled Y-parameters which are in good agreement with the measured Y-parameters from 0.5 to 20GHz.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.179-184
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• 2023

We propose the modeling methodology of CMOS inverter made of LTPO TFT using a machine learning. LTPO can achieve advantages of LTPS TFT with high electron mobility as a driving TFT and IGZO TFT with low off-current as a switching TFT. However, since the unified model of both LTPS and IGZO TFTs is still lacking, it is necessary to develop a SPICE-compatible compact model to simulate the LTPO current-voltage characteristics. In this work, a generic framework for combining the existing formula of I-V characteristics with artificial neural network is presented. The weight and bias values of ANN for LTPS and IGZO TFTs is obtained and implemented into PSPICE circuit simulator to predict CMOS inverter. This methodology enables efficient modeling for predicting LTPO TFT circuit characteristics.

• Journal of Electrical Engineering and Technology
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• v.10 no.1
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• pp.205-215
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• 2015

Common mode (CM) conducted interference are predicted and compared with experiments in a motor drive system of Electric vehicles in this study. The prediction model considers each part as an equivalent circuit model which is represented by lumped parameters and proposes the parameter extraction method. For the modeling of the inverter, a concentrated and equivalent method is used to process synthetically the CM interference source and the stray capacitance. For the parameter extraction in the power line model, a computation method that combines analytical method and finite element method is used. The modeling of the motor is based on measured date of the impedance and vector fitting technique. It is shown that the parasitic currents and interference voltage in the system can be simulated in the different parts of the prediction model in the conducted frequency range (150 kHz-30 MHz). Experiments have successfully confirmed that the approach is effective.

• Proceedings of the KIPE Conference
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• 2016.07a
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• pp.309-310
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• 2016

Sealed flooded lead acid batteries are becoming popular in the industry because of their low cost as compared to their counterparts. State of Charge (SOC) estimation has always been an important factor in battery management systems. For the accurate SOC estimation, open circuit voltage (OCV) hysteresis should be modelled accurately. The hysteresis phenomenon of the sealed flooded lead acid battery is discussed in detail and its ultimate modeling is proposed based on the conventional parallelogram method. The SOC estimation is performed by using Unscented Kalman Filter (UKF) while the parameters of the battery are estimated using Auto Regressive with external input (ARX) method. The validity of the proposed method is verified by the experimental results. The SOC estimation error by the proposed method is less than 3 % all wing the 125hr test.

• 한국신재생에너지학회:학술대회논문집
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• 2005.06a
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• pp.127-131
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• 2005

The paper addresses modeling and analysis of a grid-connected photovoltaic generation system (PV system). PSCAD/EMIDC. an industry standard simulation tool for studying the transient behavior of electric power system and apparatus. is used to conduct all aspects of model implementation and to carry out extensive simulation study. An equivalent circuit model of a solar cell has been used for modeling solar array. A PWM voltage source inverter (VSI) and its current control scheme have been implemented. A maximum power point tracking (MPPT) technique is employed for drawing the maximum available energy from the PV array. Comprehensive simulation results are presented to examine PV array behaviors and PV system control performance in response to irradiation changes. In addition, dynamic responses of PV array and system to network fault conditions are simulated and analysed

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.2
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• pp.88-93
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• 2007

In this paper, a simple and improved noise parameter model of RF MOSFETs is developed and verified. Based on the analytical model of channel thermal noise, closed form expressions for four noise parameters are developed from proposed equivalent small signal circuit. The modeling results show a excellent agreement with the measured data of $0.13{\mu}m$ CMOS devices.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.11
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• pp.1601-1605
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• 2012

Three-phase voltage and current is applied to the three-phase alternating current motors which are commonly used in industry. Three phase variables of a, b, c are converted into d, q, 0 axis and the AC machines are modeled and analyzed. Basically the coordinate transformation or d-q transformation is used for convenience, a few steps are needed to analyze the motor performances - separating d and q components, establishing each equivalent circuit, and solving the differential equations of the circuits. In this study, a modeling technique of induction motor using complex vector is proposed and it can explain the induction motor physically. This method does not need the separating process of d and q components. With this technique, the model becomes simple, is easy to understand in physical, and can get the same results with those from the other models. These simulation results of the proposed model are compared with them for the conformation of the proposed method.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.864-865
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• 2008

This paper deals with d-q axis inductance measurements of IPMSM considering core loss at low speed. d-q axis inductance measurements generally are conducted at rated speed and parallel core loss model can be used to exclude core loss effects on inductances. Core loss is generally modeled parallel to input terminal of d-q axis equivalent circuit. Therefore, the effect of core loss on inductance calculation can be varied by core loss modeling. In this paper, d-q axis inductance is calculated parallel and series core loss modeling. Calculated inductances are compared to FEA results and it is concluded that series core loss modeling is more closed to FEA results at low speed.