• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.879-882
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• 2003

Differential Power Analysis(DPA) is powerful attack method for smart card. Self-timed circuit has several advantages resisting to DPA. In that reason, DPA countermeasure using self-timed circuit is thought as one of good solution for DPA prevention. In this paper, we examine what self-timed features are good against DPA, and how much we can get benefit from it. Also we test several self-timed circuit implementation style in order to compare DPA resistance factor. Simulation results show that self-timed circuit is more resistant to DPA than conventional synchronous circuit, and can be used for designing cryptographic hardware for smart-card.

• Journal of Korea Society of Digital Industry and Information Management
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• v.8 no.1
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• pp.107-115
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• 2012

This paper proposes on the structure for reducing the circuit area and increasing the computation speed in implementing to hardware using the SEED algorithm of a 128-bit block cipher. SEED cipher can be implemented with S/W or H/W method. It should be important that we have minimize the area and computation time in H/W implementation. To increase the computation speed, we used the structure of the pipelined systolic array, and this structure is a simple thing without including any buffer at the input and output circuit. This circuit can record the encryption rate of 320 Mbps at 10 MHz clock. We have designed the circuit with the Verilog HDL coding showing the circuit performances in the figures and the table.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.177-183
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• 2015

A high speed VLSI digital Winner-Take-All (WTA) circuit called simultaneous digital WTA (SDWTA) circuit is presented in this paper. A minimized comparison-cell (w-cell) is developed to reduce the size and to achieve high-speed. The w-cell which is suitable for VLSI implementation consists of only four transistors. With a minimized comparison-cell structure SDWTA can compare thousands of data simultaneously. SDWTA is scalable with O(mlog n) time-complexity for n of m-bit data. According to simulations, it takes 16.5 ns with $1.2V-0.13{\mu}m$ process technology in finding a winner among 1024 of 16-bit data.

• 전기의세계
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• v.28 no.9
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• pp.51-59
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• 1979

The forming and design method of D.C thyristor chopper circuit for DC Series motor control is suggested, ard the computation method of thyristor commutaing element's, value which makes it all the more important, is possible. Also the trigger circuit was dealt with. In this paper, in order to control the duty cycle, the duty time is kept on constancy and variable chopping frequency was adopted. By above mentioned circuit design method, the D.C thyristor chopper circuit was implemented and tested. In this circuit, the result of D.C motor control was good and reliable. The relation between the $K_{d}$ and the ratio of input-output current, or the characteristic of speed was varied lineary at the range 0.1 ~ 0.9 of duty cycle. This confirms the fact that D.C to D.C power conversion which is the merit of chopper control is operated most likely a transformer.ormer.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.10a
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• pp.469-471
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• 2022

This paper presents an implementation of a calibration circuit to correct the gain error, DC offset and sampling clock phase error generated in the process of converting digital pixels to analog pixels to drive an analog-driven 4K UHD LCOS panel. The proposed calibration circuit consists of a gain and DC offset adjustment circuit and a sampling clock phase adjustment circuit. The calibration circuit is implemented with an FPGA device, and video amplifiers.

• The Journal of the Korea institute of electronic communication sciences
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• v.5 no.1
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• pp.17-22
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• 2010

Generally, there are Chua's Circuit, Lorenz Circuit and Duffing circuit in the chaos circuit. Among these chaos circuits, Chua's circuit is well known to make the electronic parts easily. Chua's circuit is the constitute of the linearelements. These are constitute of Resistor component(R), inductor component(L), capacitor(C), and nonlinear element which is constitute of nonlinear resistor. However, L element have a difficult problem to implement real hardware by using commercial parts. Due to this, it has a saturation characteristic. In this paper, we analyzed the simplified Chua's circuit which is replace L to C by PSPICE program. Because L element has a difficult problem to make a real hardware, L has a saturation characteristic and we also confirm this analysis as the result.

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.299-302
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• 1999

An analog implementation of space vector PWM is proposed in this paper. It is shown that a space vector PWM can be implemented by adding a zero sequency voltage to reference voltage of triangle comparison PWM. The proposed scheme is implemented by six diodes and, an operational amplifier circuit and, a few resistors.

• Proceedings of the IEEK Conference
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• 2001.06e
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• pp.43-46
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• 2001

This paper has been studied a implementation Home Automation by PLM and Telephone system. The PLM is composed of FSK IC-chip and the circuit for the power line communication. In this paper load control was made with PIC16F84A and its communication speed was 1200 baud rates.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.10
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• pp.2373-2379
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• 2015

COMS(Communication, Ocean and Meteorological Satellite), the first Korean geostationary meteorological satellite, provides free meteorological information through HRIT/LRIT(High/Low Rate Information Transmission) service. This work presents the development of data receiver circuit that is essential to the implementation of a low-cost meteorological information receiver system. The data receiver circuit processes the data units according to the specification of physical layer and data link layer of HRIT/LRIT service. For this purpose, the circuit consists of a Viterbi decoder, a sync. word detector, a derandomizer, a Reed-Solomon decoder and so on. The circuit also supports PCI express interface to pass the information data on to the host PC. The circuit was implemented on an FPGA(field programmable gate array) and its function was verified through simulations and hardware implementation.

• The Journal of Engineering Research
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• v.2 no.1
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• pp.31-37
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• 1997

This paper describes the design and implementation of 8 bit ALU graphic simulator which helps students who study the structure and operation course of general ALU. ALU of this paper consists of three parts, arithmetic circuit, logic circuit, and shifter. Each of them performs as follows. Arithmetic circuit performs arithmetic operation such as addition, subtraction, 1 increment, 1 decrement, 2's complement, logic circuit performs logic operation such as OR, AND, XOR, NOT, and shifter performs shift operation and transfers the result of circuits of arithmetic, logic to data bus. The instructions which relate to these basic ALU functions was selected from Z80 instructions and ALU circuit was designed with those instructions and this designed ALU circuit was implemented on graphic screen. And all state of this data operation course in ALU was showed by bit and logic gate unit.