• Transactions of the Korean Society of Mechanical Engineers
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• v.19 no.11
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• pp.3072-3083
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• 1995

The numerical simulation on the three-dimensional natural convection heat transfer in the enclosure with heat generating chip is performed, and the effects of convective heat loss and vents are also examined. The effects of the Rayleigh number and outer Nusselt number (Nu$_{0}$) on the maximum chip temperature and the fractions of heat loss from the hot surfaces are investigated. The results show that conduction through the substrate is dominant in heat dissipation. With the increase of Rayleigh number, heat dissipation through the chip surfaces increases and heat loss through the substrate decreases. Maximum dimensionless temperature with vents is found to decrease about 40% compared to the one without vents at Nu$_{0}$=0.l. It is also shown that effects of size and location of the vents are negligible.ble.

• Journal of the Korean Ceramic Society
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• v.29 no.12
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• pp.956-962
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• 1992

The predominant sintering mechanisms of low firing temperature ceramic substrate which consists of borosilicate glass containing alumina as a filler are the rearrangement of alumina particles and the viscous flow of glass powders. In this system, sintering condition depends on the volume ratio of alumina to glass and on the particle size. When the substrate contains about 35 vol% alumina filler and the average alumina particle size is 4 $\mu\textrm{m}$, the best firing condition is obtained at the temperature range of 900∼1000$^{\circ}C$. The extensive rearrangement behavior occurs at these conditions, and the optimum sintering condition is attained by smaller size of glass particles, too. The formation of cristobalite during sintering causes the difference of thermal expansion coefficient between the substrate and Si chip. This phenomenon degradates the capacity of Si chip. Therefore, the crystallization should be prevented. In the alumina filled borosilicate glass system, the crystallization does not occur. This effect may have some relation with aluminum ions in alumina. For aluminum ions diffuse into glass matrix during sintering, functiong as network former.

• Journal of Welding and Joining
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• v.20 no.2
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• pp.90-94
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• 2002

FC-BGA has advantages over other interconnection methods including high I/O counts, better electrical performance, high throughput, and low profile. But, FC-BGA has a lot of reliability issues. The 2nd level solder joint reliability of the FC-BGA with large chip on laminate substrate was studied in this paper. The purpose of this study is to discuss solder joint failures of 2nd level thermal cycling test. This work has been done to understand the influence of the structure of package, the properties of underfill, the properties and thickness of bismaleimide tiazine substrate and the temperature range of thermal cycling on 2nd level solder joint reliability. The increase of bismaleimide tiazine substrate thickness applied to low modulus underfill was improve of solder joint reliability. The resistance of solder ball fatigue was increased solder ball size in the solder joints of FC-BGA.

• Journal of the Semiconductor & Display Technology
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• v.4 no.2 s.11
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• pp.33-37
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• 2005

Bare-chip packaging becomes more popular along with the miniaturization of IT components. In this paper, we have studied flip-chip process, and developed automated bonding system. Among the several bonding method, NCP bonding is chosen and batch-type equipment is manufactured. The dual optics and vision system aligns the chip with the substrate. The bonding head equipped with temperature and force controllers bonds the chip. The system can be easily modified fer other bonding methods such as ACF.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.09a
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• pp.183-192
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• 2001

1- Buildup PCB technology is utilized to a bare chip attach substrate technology for packaging of semiconductor chip 2- Requirement for the substrate design rule is described in SIA International Technology Roadmap for Semiconductor. 3- There are seven fabrication methods of build-up technology. 4- Coating and lamination for resin and photo, and laser for micro via hope processes are available. Below $50\mu\textrm{m}$ in diameter is possible. 5- Fine pitch lines down to $30\mu\textrm{m}$ can be achieved by pattern plating with better electrical property. 6- Dielectric loss reduction is a key material improvement item for next generation build-up technology. 7- High band width up to 512 GB/s is possible with current wiring groundrule.

• Journal of the Microelectronics and Packaging Society
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• v.26 no.4
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• pp.47-53
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• 2019

Stiffness-gradient stretchable electronic packages of the soft PDMS/hard PDMS/PTFE structure were processed using the polydimethylsiloxane (PDMS) as the base substrate and the more stiff polytetrafluoroethylene (PTFE) as the island substrate, and their stretchable deformation-resistance characteristics were characterized. The flip-chip joints, formed by bonding the chip bumps of 50 ㎛-diameter onto the PDMS/PTFE substrate pads, exhibited an average contact resistance of 96 mΩ. When the stretchable package of the soft PDMS/hard PDMS/PTFE structure was deformed to 30% elongation, the strain on the PTFE was restrained to 1%, resulting in a negligible resistance increase of 1% in the daisy-chain circuit formed on the PTFE island substrate. The circuit resistance increased for 1.7% after 2,500 cycles of 0~30% stretchable deformation.

• Journal of agriculture & life science
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• v.44 no.5
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• pp.9-13
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• 2010

This study was conducted to identify the possibility of utilization of coconut substrates for nutrition culture of cut-chrysanthemum. The materials of substrate were composed of dust, fiber, and chip from coco-nut fruit. Dust was used in dust (100%), and dust+chip and +fiber were used in the ratio of 7:3 (v:v), respectively, as coconut mixture substrate. Perlite was used as control in this experiment. Water content in the perlite medium was lower than in dust substrate. The pH of all coconut substrates ranged from 6.5 to 5.8, whereas perlite substrate ranged from 7.3 to 6.7. While, EC of dust substrates shown to be highest but perlite substrate was lowest. The growth of chrysanthemum such as stem length, leaf area, and dry matter showed better results in coconut substrates than that of perlite and dust. However, there was no differences days to in flowering among treatments.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.28 no.4
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• pp.435-442
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• 2004

This paper presents a hermetic MEMS on-chip package bonded by a closed-loop AuSn solder-line. We design three different package specimens, including a substrate heated specimen without interconnection-line (SHX), a substrate heated specimen with interconnection-line (SHI) and a locally heated specimen with interconnection-line (LHI). Pressurized helium leak test has been carried out for hermetic seal evaluation in addition to the critical pressure test for bonding strength measurement. Substrate heating method (SHX, SHI) requires the bonding time of 40min. at 400min, while local heating method (LHI) requires 4 min. at the heating power of 6.76W. In the hermetic seal test. SHX, SHI and LHI show the leak rates of 5.4$\pm$6.7${\times}$$^{-10}$ mbar-l/s, 13.5$\pm$9.8${\times}$$^{-10}$ mbar-l/s and 18.5$\pm$9.9${\times}$$^{-10}$ mbar-l/s, respectively, for an identical package chamber volume of 6.89$\pm$0.2${\times}$$^{-10}$. In the critical pressure test, no fracture is found in the bonded specimens up to the applied pressure of 1$\pm$0.1MPa, resulting in the minimum bonding strength of 3.53$\pm$0.07MPa. We find that the present on-chip packaging using a closed AuSn solder-line shows strong potential for hermetic MEMS packaging with interconnection-line due to the hermetic seal performance and the shorter bonding time for mass production.

• Journal of the Korean Institute of Intelligent Systems
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• v.23 no.4
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• pp.286-291
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• 2013

In this paper, in-line type flip chip bump 3D inspection equipment, using white light interferometer with large F.O.V., which is aimed to be used in flip chip bump test process is developed. Results of flip chip bump height measurement in many substrates and repeatability test results for the bumps in fixed location of each substrate are shown. Test results from test bench and those from developed flip chip bump 3D inspection equipment are compared and as a result repeatability is improved by reducing the impact of system vibration. A valuation basis for the testing quality of flip chip bump 3D inspection equipment is proposed.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.4
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• pp.149-154
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• 2018

This paper describes the fabrication and heat transfer property of 50 watts rated LED array module where multiple chips are mounted on chip-on-board type ceramic-metal hybrid substrate with high heat dissipation property for high power street and anti-explosive lighting system. The high heat transfer ceramic-metal hybrid substrate was fabricated by conformal coating of thick film glass-ceramic and silver pastes to form insulation and conductor layers, using thick film screen printing method on top of the high thermal conductivity aluminum alloy heat-spreading panel, then co-fired at $515^{\circ}C$. A comparative LED array module with the same configuration using epoxy resin based FR-4 PCB with thermalvia type was also fabricated, then the thermal properties were measured with multichannel temperature sensors and thermal resistance measuring system. As a result, the thermal resistance of the ceramic-metal hybrid substrate in the $4{\times}9$ type LEDs array module exhibited about one third to the value as that of FR-4 substrate, implying that at least triple performance of heat transfer property as that of FR-4 substrate was realized.