• 마이크로전자및패키징학회지
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• 제7권1호
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• pp.61-73
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• 2000

In traditional electronic packages the die and the substrate are interconnected with fine wire. Wire bonding technology is limited to bond pads around the peripheral of the die. As the demand for I/O increases, there will be limitations with wire bonding technology.

• 대한기계학회논문집A
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• 제32권9호
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• pp.720-727
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• 2008

Microfluidic single chip integrating thermopneumatic micropump and micro check valve are developed. The micropump and micorvalve are made of biocompatible materials, glass and PDMS, so as to be applicable to the biochip. By using the passive-type check valve, backward flow and fluid leakage are blocked and flow control is stable and precise. The chip is composed of three PDMS layers and a glass substrate. In the chip, flow channel and pump chamber were made on the PDMS layers by the replica molding technique and pump heater was made on the glass substrate by Cr/Au deposition. Diameter of the pump chamber is 7 mm and the width and depth of the channel are 200 and $180{\mu}m$, respectively. The PDMS layers chip and the heater deposited glass chip are combined by a jig and a clamp for pumping operation, and they are separable so that PDMS chip is used as a disposable but the heater chip is able to be used repeatedly. Pumping performance was simulated by CFD software and investigated experimentally. The performance was the best when the duty ratio of the applied voltage to the heater was 33%.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2005년도 춘계학술대회 논문집
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• pp.1206-1209
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• 2005

In recent, injection molding process for features in sub-micron scale is under active development as patterning nano-scale features, which can provide the master or stamp for molding, and becomes available around the world. Injection molding has been one of the most efficient processes for mass production of the plastic product, and this process is already applied to nano-technology products successfully such as optical storage media like DVD or BD which is a large area plastic thin substrate with nano-scale features on its surface. Bio chip for like DNA sequencing may be another application of this plastic substrate. The DNA can be sequenced using order of 100 nm pore structure when making the DNA flow through the pore structure. Agarose gel and silicon based chip have been used to sequence the DNA, but injection molded plastic chip may have benefit in terms of cost. This plastic DNA sequencing chip has plenty of pillars in order of 100 nm in diameter on the substrate. When the usual features in case of DVD or BD have very low aspect ratio, even less than 0.5, but the DNA chip will have relatively high aspect ratio of about 2. It is not easy to injection mold the large area thin substrate with sub-micron features on its surface due to the characteristics of the molding process and it becomes much more difficult when the aspect ratio of the features becomes high. We investigated the effect of the molding parameters for injection molding with high aspect ratio nano-scale features and injection molded some plastic DNA sequencing chips. We also fabricated PR masters and Ni stamps of the DNA chip to be used for molding

• 전자공학회논문지A
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• 제32A권3호
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• pp.89-99
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• 1995

In this paper, we ecamined the effect that MCM-L technique influencess on the design and fabrication of multichip memory modules in increasing the packing desity of memory capacity and maximizing its electrical characteristics. For that purpose, we examined the effective methods of reducing the area of module layout and the wiring length with the variation of chip allocation and the number of wiring layers. We fabricated a 256K${\times}$8bit SRAM module with eight 32K${\times}$8bit SRAM chips. The routing experiment showed that we could optimize the area of module layout and wiring length by placing chips in a row, arranging module I/O pads parallel to chip I/O pads, and equalizing the number of terminal sides of module I/O's to that of chip I/O's. The routing was optimized when we used three wire layers in case of one sided chip mounting or five wire layers in case of double sided chip mounting. The fabricated modules showed 18.9 cm/cm$^{2}$ in wiring density, 65 % in substrate occupancy efficiency, and module substrate and functionally tested to find out the module working perfectly.

• 한국산학기술학회논문지
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• 제13권10호
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• pp.4757-4761
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• 2012

알루미늄 기판 및 양극산화 공정을 사용하여 LED Chip on Board(COB) 패키지를 제작하였다. 선택적 양극산화 공정을 적용하여 알루미늄 기판 상에 알루미나를 형성하고 이를 COB 패키지 절연층으로 사용하였으며, 비아홀 내부가 충진된 구조의 Thermal Via를 구현하였다. 패키지 기판 종류에 따른 열저항 및 발광효율 변화를 파악하기 위해 알루미늄 기판과 알루미나 기판을 제작하고 이를 각각 비교 분석하였다. Thermal Via가 적용된 알루미늄 기판이 51%의 열저항 개선 및 14%의 발광효율 향상 특성을 보여주었다. 이러한 결과는 선택적 양극산화 공정 및 Thermal Via 구조적용으로 COB 패키지의 방열 특성이 향상되었음을 의미한다. 또한 동일한 전력 소모시 LED 칩 개수에 따른 COB 패키지의 열저항 및 발광효율 변화를 분석함으로써 다수 칩의 효율적인 배치가 열저항 및 발광효율을 증가시킬 수 있음을 확인하였다.

• 한국공작기계학회논문집
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• 제16권5호
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• pp.134-139
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• 2007

This paper presents a computer-based analysis on the thermal shock characteristics of Pb-free solder joints and UBM in flip chip assemblies. Among four types of popular UBM systems, TiW/Cu system with 95.5Sn-3.9Ag-0.6Cu solder joints was chosen for simulation. A simple 3D finite element model was first created only including silicon die, mixture between underfill and solder joints, and substrate. The displacements due to CTE mismatch between silicon die and substrate was then obtained through FE analysis. Finally, the obtained displacements were applied as mechanical loads to the whole 2D FE model and the characteristics of flip chip assemblies were analyzed. In addition, based on the hyperbolic sine law, the accumulated creep strain of Pb-free solder joints was calculated to predict the fatigue life of flip chip assemblies under thermal shock environments. The proposed method for fatigue life prediction will be evaluated through the cross check of the test results in the future work.

• 마이크로전자및패키징학회지
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• 제20권4호
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• pp.53-58
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• 2013

An innovative packaging solution, Flip Chip with Copper (Cu) Column bond on lead (BOL) Enhanced Process (fcCuBE$^{(R)}$) delivers a cost effective, high performance packaging solution over typical bond on capture pad (BOC) technology. These advantages include improved routing efficiency on the substrate top layer thus allowing conversion functionality; furthermore, package cost is lowered by means of reduced substrate layer count and removal of solder on pad (SOP). On the other hand, as electronic packaging technology develops to meet the miniaturization trend from consumer demand, reliability testing will become an important issue in advanced technology area. In particular, electromigration (EM) of flip chip bumps is an increasing reliability concern in the manufacturing of integrated circuit (IC) components and electronic systems. This paper presents the results on EM characteristics on BOL and BOC structures under electrical current stressing in order to investigate the comparison between two different typed structures. EM data was collected for over 7000 hours under accelerated conditions (temperatures: $125^{\circ}C$, $135^{\circ}C$, and $150^{\circ}C$ and stress current: 300 mA, 400 mA, and 500 mA). All samples have been tested without any failures, however, we attempted to find morphologies induced by EM effects through cross-sectional analysis and investigated the interfacial reaction characteristics between BOL and BOC structures under current stressing. EM damage was observed at the solder joint of BOC structure but the BOL structure did not show any damage from the effects of EM. The EM data indicates that the fcCuBE$^{(R)}$ BOL Cu column bump provides a significantly better EM reliability.

• International Journal of Internet, Broadcasting and Communication
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• 제7권2호
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• pp.161-167
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• 2015

The performance of high power LEDs highly depends on the junction temperature. Operating at high junction temperature causes elevation of the overall thermal resistance which causes degradation of light intensity and lifetime. Thus, appropriate thermal management is critical for LED packaging. The main goal of this research is to improve thermal resistance by optimizing and comparing nano-pore silicon-based thermal substrate to insulated metal substrate and direct bonded copper thermal substrate. The thermal resistance of the packages are evaluated using computation fluid dynamic approach for 1 W single chip LED module.

• 센서학회지
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• 제26권6호
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• pp.386-390
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• 2017

A $5^{th}$-order low-pass filter (LPF) chip implemented in a six-layer low-temperature co-fired ceramic (LTCC) dielectric substrate has been presented. Lumped elements constituting the LPF are designed three-dimensionally in multilayers. In order to improve the parasitic and mutual coupling effects between them, the LPF is designed by sequentially integrating the three-dimensional (3D) lumped elements, by comparing it to the results of the schematic circuit and 3D electromagnetic (EM) analysis. The designed 3D LPF chip was fabricated in a six-layer LTCC substrate as small as $4.0{\times}3.22{\times}0.68mm^3$. The measured return and insertion losses are less than -11 dB and -0.61 dB, respectively, below 1.5 GHz.

• 한국광학회지
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• 제16권3호
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• pp.275-286
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• 2005

InGaN LED에서 칩 구조 및 칩마운트 구조에 따른 광추출효율의 변화를 Monte Calo 기법을 이용하여 해석하였다. Simulation을 통해 얻은 중요한 결론의 하나는, InGaAlP 또는 InGaN/SiC LED의 경우에서는 달리, InGaN/sapphire LED의 경우 칩의 측 벽면 기울임 기법의 광추출효율 개선효과가 상대적으로 미미하다는 점이다. InGaN/SiC LED의 경우와는 달리, 기판으로 사용되는 sapphire의 굴절률이 상대적으로 작아서 생성된 광자들이 기판으로 넘어가는데 전반사장벽을 만나게 되어, 많은 광자들이 기판으로 넘어가지 못하고 두께가 매우 얇은 반도체 결정층에 갇히는 현상 때문이다. 동일한 현상은 epi-down 구조의 칩 마운트에서 광추출효율이 크게 개선되지 못하는 원인으로도 작용하게 된다. 광추출효율 관점에서의 epi-down 구조의 InGaN/sapphire LED가 갖고 있는 잠재력을 살리기 위한 방법의 하나는 기판-에피택시 계면을 texturing 하는 것이라고 할 수 있는데, 이 경우 생성된 광자들이 다량기판으로 넘어갈 수 있게 되어 광추출효율이 현저하게 개선된다.