• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.12 s.354
• /
• pp.23-32
• /
• 2006

Fast and accurate power bus design (FAPUD) method for multi-layers high-speed digital boards is devised for the power supply network design tool for accurate and precise high speed board. FAPUD is constructed, based on two main algorithms of the PBEC (Path Based Equivalent Circuit) model and the network synthesis method. The PBEC model exploits simple arithmetic expressions of the lumped 1-D circuit model from the electrical parameters of a 2-D power distribution network. The circuit level design based on PBEC is carried with the proposed regional approach. The circuit level design directly calculates and determines the size of on-chip decoupling capacitors, the size and the location of off-chip decoupling capacitors, and the effective inductances of the package power bus. As a design output, a lumped circuit model and a pre-layout of the power bus including a whole decoupling capacitors are obtained after processing FAPUD. In the tuning procedure, the board re-optimization considering simultaneous switching noise (SSN) added by I/O switching can be carried out because the I/O switching effect on a power supply noise can be estimated over the operation frequency range with the lumped circuit model. Furthermore, if a design changes or needs to be tuned, FAPUD can modify design by replacing decoupling capacitors without consuming other design resources. Finally, FAPUD is accurate compared with conventional PEEC-based design tools, and its design time is 10 times faster than that of conventional PEEC-based design tools.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.9
• /
• pp.14-23
• /
• 2010

This paper reports the fabrication of a DVB-T/H System in Package (SiP) that is able to receive and process the DVB-T/H signal. The DVB-T/H is the European telecommunication standard for Digital Video Broadcasting (DVB). An IC-embedded Printed Circuit Board (PCB) process, interpose a chip between PCB layers, has applied to the DVB-T/H SiP. The chip inserted in DVB-T/H SiP is the System on Chip (SoC) for mobile TV. It is comprised of a RF block for DVB-T/H RF signal and a digital block to convert received signal to digital signal for an application processor. To operate the DVB-T/H IC, a 3MHz DC-DC converter and LDO are on the DVB-T/H SiP. And a 38.4MHz crystal is used as a clock source. The fabricated DVB-T/H SiP form 4 layers which size is $8mm{\times}8mm$. The DVB-T/H IC is located between 2nd and 3rd layer. According to the result of simulation, the RF signal sensitivity is improved since the layout modification of the ground plane and via. And we confirmed the adjustment of LC value on power transmission is necessary to turn down the noise level in a SiP. Although the size of a DVB-T/H SiP is decreased over 70% than reference module, the power consumption and efficiency is on a par with reference module. The average power consumption is 297mW and the efficiency is 87%. But, the RF signal sensitivity is declined by average 3.8dB. This is caused by the decrease of the RF signal sensitivity which is 2.8dB, because of the noise from the DC-DC converter.

• Korean Journal of Materials Research
• /
• v.29 no.7
• /
• pp.437-442
• /
• 2019

Green $BaSi_2O_2N_2:0.02Eu^{2+}$ phosphor is synthesized through a two-step solid state reaction method. The first firing is for crystallization, and the second firing is for reduction of $Eu^{3+}$ into $Eu^{2+}$ and growth of crystal grains. By thermal analysis, the three-time endothermic reaction is confirmed: pyrolysis reaction of $BaCO_3$ at $900^{\circ}C$ and phase transitions at $1,300^{\circ}C$ and $1,400^{\circ}C$. By structural analysis, it is confirmed that single phase [$BaSi_2O_2N_2$] is obtained with Cmcm space group of orthorhombic structure. After the first firing the morphology is rod-like type and, after the second firing, the morphology becomes round. Our phosphor shows a green emission with a peak position of 495 nm and a peak width of 32 nm due to the $4f^65d^1{\rightarrow}4f^7$ transition of $Eu^{2+}$ ion. An LED package (chip size $5.6{\times}3.0mm$) is fabricated with a mixture of our green $BaSi_2O_2N_2$, and yellow $Y_3Al_5O_{12}$ and red $Sr_2Si_5N_8$ phosphors. The color rendering index (90) is higher than that of the mixture without our green phosphor (82), which indicates that this is an excellent green candidate for white LEDs with a deluxe color rendering index.