• Korean Journal of Food Science and Technology
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• v.19 no.2
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• pp.129-133
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• 1987

To develop a microcomputer-based data acquisition system for measurement of variables such as temperature and weight in food process, a low-cost data acquisition system was developed using an Apple II microcomputer. The system consisted of a microcomputer, a temperature sensor made of pt-100, a strain gauge load cell for weighing, a preamplifier for signal conditionings and an interface device. Interface device was built with programmable interface chip MC 6821, tristate buffer 74244 and analog-to-digital converter ADC 0809. The analog signals of temperature and weight were serially acquisited upon the program. The BASIC language was used for operating the data acquisition and data handling programs. The system successfully measured the variables such as temperature and weight with various sampling intervals in food dehydration process.

• Transactions of Materials Processing
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• v.17 no.8
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• pp.594-599
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• 2008

This paper presents a micro air pump based on the synthetic jet to supply reactant at the cathode side for micro fuel cells. The synthetic jet is a zero mass flux device that converts electrical energy into the momentum. The synthetic jet actuation is usually generated by a traditional PZT-driven actuator, which consists of a small cylindrical cavity, orifices and PZT diaphragms. Therefore, it is very important that the design parameters are optimized because of the simple configuration. To design the synthetic jet micro air pump, a numerical analysis has been conducted for flow characteristics with respect to various geometries. From results of numerical analysis, the micro air pump has been fabricated by the PDMS replication process. The most important design factors of the micro air pump in micro fuel cells are the small size and low power consumption. To satisfy the design targets, we used SP4423 micro chip that is high voltage output DC-AC converter to control the PZT. The SP4423 micro chips can operate from $2.2{\sim}6V$ power supply(or battery) and is capable of supplying up to 200V signals. So it is possible to make small size controller and low power consumption under 0.1W. The size of micro air pump was $16{\times}13{\times}3mm^3$ and the performance test was conducted. With a voltage of 3V at 800Hz, the air pump's flow rate was 2.4cc/min and its power consumption was only 0.15W.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.2003-2008
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• 2012

A drive system is necessary to operate LED by an LED illumination system. Because Switched Mode Power Supply (SMPS) is higher in efficiency in the large capacity than Linear Regulator, it is used mainly and controls this in an analog form or digital method. A MCU and a DSP of the digital control central processing unit were higher in a unit price than existing analog control chip, so that an approach was not easy for application of SMPS. But it can take the earnings by it lets you integrate various digital control features like an LED illumination system in one MCU, and realizing a whole system. In this paper, we suggest the algorithm that can improve LED driving current in applying such a digital control method using low-priced type MCU.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.5C
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• pp.371-381
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• 2005

In this paper, we propose an advanced hardware architecture for the CAVLC entropy encoder/decoder engine for real time video compression. The CAVLC (Context-based Adaptive Variable Length Coding) is a lossless compression method in H.264/AVC and it has high compression efficiency but has computational complexity. The reference memory size is optimized using partitioned storing method and memory reuse method which are based on partiality of memory referencing. We choose the hardware architecture which has the most suitable one in several encoder/decoder architectures for the mobile devices and improve its performance using parallel processing. The proposed architecture has been verified by ARM-interfaced emulation board using Altera Excalibur and also synthesized on Samsung 0.18 um CMOS technology. The synthesis result shows that the encoder can process about 300 CIF frames/s at 150MHz and the decoder can process about 250 CIF frames/s at 140Mhz. The hardware architectures are being used as core modules when implementing a complete H.264/AVC video encoder/decoder chip for real-time multimedia application.

• Journal of Digital Contents Society
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• v.5 no.4
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• pp.251-256
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• 2004

The flatness of a silicon wafer concerned with ULSI chip is one of the most critical parameters ensuring high yield of wafers. That is necessary to constitute the circuit with high quality for he surface of silicon wafer, which comes to be base to make the direct circuit of the semiconductor, Flatness, therefore, is the most important factor to guarantee it wafer with high quality. The process of polishing is one of the most crucial production line among 10 processing stages to change the rough surface into the flatnees with best quality. Currently at this process, it is general for an engineer in charge to observe, judge and control the model of wafer from the monitor of measuring equipment with his/her own eyes to enhance the degree of flatness. This, however, is quite a troublesome job for someone has to check of process by one's physical experience. The purpose of this study is to approach the model of wafer with digital contents and to apply the result of the research for an algorithm which enables to control the polishing process by means of measuring the degree of flatness automatically, not by person, but by system. In addition, this paper shows that this algorithm proposed for the whole wafer flatness enables to draw an estimated algorithm which is for the thickness of sites to measure the degree of flatness for each site of wafer.

• Korean Journal of Optics and Photonics
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• v.27 no.4
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• pp.127-132
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• 2016

In this paper, a trench structure was fabricated by femtosecond-laser machining to eliminate thermal crosstalk in a multichannel variable optical attenuator (VOA), to prevent decreasing attenuation efficiency of the VOA. Trenches of a variety of widths and depths were fabricated on the VOA chips by femtosecond-laser processing. After the machining, attenuation according to current change was observed in each VOA chip module with trenches. As a result, we could observe high responsivity of attenuation and low power consumption, and that the heat of each channel barely influenced other channels.

• Korean Journal of Crystallography
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• v.14 no.1
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• pp.1-6
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• 2003

NiZn-ferrites were synthesized from the waste catalysts. which were by product of styrene monomer process and buried underground as an industrial wastes, and their magnetic properties were investigated. Nickel oxide and zinc oxide powders were mixed with finely ground waste catalysts, and spinel type ferrite was obtained by calcination at 900℃ and sintering at 1325℃ for 5 hours. The initial permeabilities were measured and reflection losses were calculated from S-parameters for the composition of Ni/sub x/Zn/sub 1-x/Fe₂O₄(x=0.36, 0.50, 0.66) and (Ni/sub 0.5/Zn/sub 0.5)/sub 1-y/Fe/sub 2+y/O₄(y=-0.02, 0, 0.02).

• Journal of the Korea Society of Computer and Information
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• v.11 no.2 s.40
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• pp.159-167
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• 2006

Lipreading has been suggested as one of the methods to improve the performance of speech recognition in noisy environment. However, existing methods are developed and implemented only in software. This paper suggests a hardware design for real-time lipreading. For real-time processing and feasible implementation, we decompose the lipreading system into three parts; image acquisition module, feature vector extraction module, and recognition module. Image acquisition module capture input image by using CMOS image sensor. The feature vector extraction module extracts feature vector from the input image by using parallel block matching algorithm. The parallel block matching algorithm is coded and simulated for FPGA circuit. Recognition module uses HMM based recognition algorithm. The recognition algorithm is coded and simulated by using DSP chip. The simulation results show that a real-time lipreading system can be implemented in hardware.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.3
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• pp.378-390
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• 2001

In this paper, it is analyzed that the error performance of a Multi-Carrier DS-CDMA system in a single cell with multipath Rician fading and multiple access interference (MAI) and the error performance of the system is compared with that of a Sing1e-Carrier DS-CDMA system. Moreover, the convolutional coding techniques with code rate of 1/2, 1/3, and 1/4 are adopted in order to improve the error performance degraded by the multipath fading and MAI and performance improvement through the coding techniques is analyzed. As a result, it is shown that the number of users in each system can be determined by the number of branches of the rake receiver in a Single-Carrier DS-CDMA system and the number of carriers in a Multi-Carrier DS-CDMA system. Furthermore, the convolutional coding should be chosen with considering the trade-off between coding gain and a power limitation in a Multi-Carrier DS-CDMA system. In case of increasing the number of carriers, the processing gain is decreased but the error performance is improved through the effect of frequency diversity and the system can be possibility implemented due to the low chip rate.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.7
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• pp.1442-1447
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• 2004

In this paper, a 6-Bit CMOS Folding and Interpolating AD Converter is presented. The converter is considered to be useful as an integrated part of a VLSI circuit handling both analog and digital signals as in the case of HDD or LAN applications. A built-in analog circuit for VLSI of a high-speed data communication requires a small chip area, low power consumption, and fast data processing. The proposed folding and interpolating AD Converter uses a very small number of comparators and interpolation resistors, which is achieved by cascading a couple of folders working in different principles. This reduced number of parts is a big advantage for a built-in AD converter design. The design is based on 0.25m double-poly 2 metal n-well CMOS process. In the simulation, with the applied 2.5V and a sampling frequency of 500MHz, the measurements are as follows: power consumption of 27mw, INL and DNL of $\pm$0.1LSB, $\pm$0.15LSB each, SNDR of 42dB with an input signal of 10MHz.