• Journal of Biosystems Engineering
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• v.30 no.3 s.110
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• pp.161-165
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• 2005

In this study, peeling test of the Altari radish on kimchi pre-processing system for mechanization was performed with the longitudinal plane peeling type with wider cutting blade than that of the peeled chip's. To determine the optimum cutter shape to match this plane peeling type, the peeling tests depending on variable cutting speed, rake angle and blade angle using the blade with thickness as 2 m and width as 50mm were performed, and the patterns of the peeled chips and peeling resistances were investigated. As the result of the tests, the rake angle of the blade with clean peeled surface of the Altari radish was over $45^{\circ}$, and the blade angle and rake angle with the minimum peeling resistance was $20^{\circ}\;and\;60^{\circ}$, respectively. The optimum peeling conditions were; the peeling speed 0.2m/s, blade angle $20^{\circ}$ and the rake angle $60^{\circ}$, and the peeling resistance of each blade was 15 N.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2001.06a
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• pp.89-92
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• 2001

In this paper, as a study of programmable software radio digital communication, we implemented ASK(Amplitude Shift Keying), FSK(Frequency Shift Keying), and PSK(Phase Shift Keying) modulation using programmable software(algorithm) of DSP(Digital Signal Processor). Moreover, it is possible to select one of those three modulation methods by realizing on single DSP. We adopted Motorola DSP56002 and Crystal CS4215(A/D and D/A converter) for our purpose. The DSP56002 is 24-bit and operates 20 MIPS at 40 MHz, and the CS4215 is 16-bit and supports the maximum 50 kHz sampling frequency.

• Journal of electromagnetic engineering and science
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• v.6 no.3
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• pp.147-154
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• 2006

In this paper, we propose and present implementation results of a high-speed turbo decoding algorithm. The latency caused by (de) interleaving and iterative decoding in a conventional maximum a posteriori(MAP) turbo decoder can be dramatically reduced with the proposed design. The source of the latency reduction is come from the combination of the radix-4, dual-path processing, parallel decoding, and rearly-stop algorithms. This reduced latency enables the use of the turbo decoder as a forward error correction scheme in real-time wireless communication services. The proposed scheme results in a slight degradation in bit-error rate(BER) performance for large block sizes because the effective interleaver size in a radix-4 implementation is reduced to half, relative to the conventional method. Fixed on the parameters of N=212, iteration=3, 8-states, 3 iterations, and QPSK modulation scheme, we designed the adaptive high-speed turbo decoder using the Xilinx chip (VIRTEX2P (XC2VP30-5FG676)) with the speed of 17.78 Mb/s. From the results, we confirmed that the decoding speed of the proposed decoder is faster than conventional algorithms by 8 times.

• Journal of the Optical Society of Korea
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• v.13 no.4
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• pp.434-438
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• 2009

In this paper, a 12.5-Gb/s optical transmitter is implemented using 0.13-${\mu}m$ CMOS technology. The optical transmitter that we constructed compensates temperature effects of VCSEL (Vertical cavity surface emitting laser) using auto-power control (APC) and auto-modulation control (AMC). An external monitoring photodiode (MPD) detects optical power and modulation. The proposed APC and AMC demonstrate 5$\sim$20-mA of bias-current control and 5$\sim$20-mA of modulation-current control, respectively. To enhance the bandwidth of the optical transmitter, an active feedback amplifier with negative capacitance compensation is exploited. The whole chip consumes only 140.4-mW of DC power at a single 1.8-V supply under the maximum modulation and bias currents, and occupies the area of 1280-${\mu}m$ by 330-${\mu}m$ excluding bonding pads.

• Journal of the Institute of Convergence Signal Processing
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• v.5 no.1
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• pp.40-45
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• 2004

This paper presents the parallel distributed control scheme for shaping of the bent glass. The designed system consists of a PC, a main controller and 11 servo-controllers, the precision motion controllers. Each elements are connected by using RS-232C and 8-bit data bus. In order to guarantee the stability and the control performance, we use a precision PID motion controller and a H-bridge on the servo-drivers. PC calculates position values of 11 DC motors by using the pre-determined curvature value and offers the user interface environment operator. The main controller provides the control instructions and parameter values to 11 servo-controllers by chip enable signal, simultaneously. Using the received commands and parameter values, the servo-controllers control the positions of the DC motors based on PID control scheme.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.11a
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• pp.193-198
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• 1999

In the 21th century, everyone feels that the multimedia system is close at hand in real life due to the rapid advance of the computer processing ability and high speed and high guality of communication services. Also the limited frequencies resource will be optimized due to rapid advances in digital video technology which is believed superior to analogue technology in information engineering. MEPG-2 has been introduced for broadcasting use such as digital TV Thus it features the high-definition and hyper-low bit rate. But, because of much throughput it has been implemented by high-priced private ASIC chip and is not in general use yet. But in this research, noticing the rapid enhancement of PC processor performance comparing with the price. MPEG-2 was developed by real time software MPEG-2 had been known impossible to implement with S/W, but the research proved the possibility of the S/W implementation and below are the pictures also in the research was improved 'Motion Vector and Compensation' Algorithm which requires the most operations and UT was made possible real time process. Multimedia Info Society has settled and accompanied by the rapid advance of image-processing technology and lots of standards.

• Journal of Information Processing Systems
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• v.8 no.3
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• pp.459-470
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• 2012

Recently, high-throughput technologies such as the two-hybrid system, protein chip, Mass Spectrometry, and the phage display have furnished a lot of data on protein-protein interactions (PPIs), but the data has not been accurate so far and the quantity has also been limited. In this respect, computational techniques for the prediction and validation of PPIs have been developed. However, existing computational methods do not take into account the fact that a PPI is actually originated from the interactions of domains that each protein contains. So, in this work, the information on domain modules of individual proteins has been employed in order to find out the protein interaction relationship. The system developed here, WASPI (Web-based Assistant System for Protein-protein interaction Inference), has been implemented to provide many functional insights into the protein interactions and their domains. To achieve those objectives, several preprocessing steps have been taken. First, the domain module information of interacting proteins was extracted by taking advantage of the InterPro database, which includes protein families, domains, and functional sites. The InterProScan program was used in this preprocess. Second, the homology comparison with the GO (Gene Ontology) and COG (Clusters of Orthologous Groups) with an E-value of $10^{-5}$, $10^{-3}$ respectively, was employed to obtain the information on the function and annotation of each interacting protein of a secondary PPI database in the WASPI. The BLAST program was utilized for the homology comparison.

• The Transactions of the Korea Information Processing Society
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• v.4 no.8
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• pp.2143-2151
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• 1997

As inter-wire spacing on a VLSI chip becomes smaller with the evolution of VLSI fabrication technology, coupling capacitance between adjacent wires is increasing rapidly over ground capacitance. Therefore, it becomes necessary to take into account the crosstalk caused mainly by coupling capacitance during the layout design of VLSI systems. This paper deals with layer assignment problem to minimize crosstalk in three layers gridded channel routing. The problem is formulated in 0/1 integer linear programming style. Upper bound for cost function is estimated for the fast termination. Experiment shows the effectiveness of our approach to minimize crosstalk.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.04b
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• pp.1619-1622
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• 2002

최근에 생산되는 디지털 VLSI칩들은 그 집적도가 계속 높아지고 있으며, 이러한 칩들을 장착한 보드의 경우도 그 복잡성이 점차 높아지고 있다. 이에 따라 칩 및 보드에 대한 철저한 테스트 과정이 요구된다. 지금까지 보드 테스트 방법으로 널리 쓰였던 ICT(In-Circuit Test)는 칩의 고집적화에 따른 핀 간격의 조밀화와 SMT(Surface Mount Technology), BGA(Ball Grid Array), MCM(Multi Chip Module) 등의 새로운 패키징 방식의 등장에 따라 테스트 방법으로의 한계성을 드러내고 있다. 이에 대한 대안으로 등장한 IEEE Std 1149.1 은 ICT의 한계성을 극복할 수 있는 기술일 뿐 아니라 여러 가지 장점을 가지고 있으며 그 활용 분야도 다양하다. 본 논문에서는 IEEE Std 1149.1에 따라 설계된 보드 상에서 발생 가능한 고장들에 대한 고장 모델을 제시한다. 또한 각 고장 모델들의 양상과 진단 기법을 제시한다. 이를 통해 IEEE Std 1149.1에 따라 설계된 보드 상에서 발생한 고장들을 검출할 수 있으며, 고장의 종류 및 성격, 그리고 고장의 발생 위치 등의 정보를 얻을 수 있다. IEEE Std 1149.1에 따른 보드 설계가 보드의 신뢰성 보장에 긴요함을 인식하는 계기가 되기를 기대하며 제시된 고장 모델 및 진단 기법이 기술적으로 중요한 참고자료가 되기를 기대한다.

• The Transactions of the Korea Information Processing Society
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• v.6 no.12
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• pp.3662-3674
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• 1999

This paper addresses some design issues for establishing the optimal number of spare units in array systems manufactured using fault-tolerant multichip modules(MCM's) for massively parallel computing(MPC). We propose a new quantitative approach to an optimal cost-effective MCM system design under yield and reliability constraints. In the proposed approach, we analyze the effect of residual redundancy on operational reliability of fault-tolerant MCM's. In particular, the issues of imperfect support circuitry, chip assembly yield and array topology are investigated. Extensive parametric results for the analysis are provided to show that our scheme can be applied to design ways using MCM's for MPC applications more efficiently, subject to yield and reliability constraints.