• 한국음향학회지
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• 제8권5호
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• pp.95-101
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• 1989

일반 DSP들은 새로운 algorithm 및 응용 system의 개발을 위해서 전용 development system 및 simulator가 필수 불가결의 요소이다. 그러나 대부분 development system은 일반화된 내부 구조에 의해 그 유연성에 한계가 존재한다. 본 연구에서는 A/D입력과 D/A출력 data를 저장하는 buffer의 길이를 program에 의해 1 sample 단위부터 최대 2K sample 단위까지 가변할 수 있도록 하고, 이들 buffer도 2중 구조로 하여 연속 신호의 처리가 가능도록 한 DSP평가용 system을 개발하였다.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2001년도 추계학술발표논문집 (하)
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• pp.1463-1466
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• 2001

본 논문은 ISDN 통신망에서 멀티미디어 통신 서비스를 제공하기 위해 단말에 사용되는 ISDN 시스템 칩 설계 및 단말 구현에 관한 것이다. 저가의 통신 단말을 구현하기 위하여 32 비트 RISC 프로세서인 ARM7 프로세서 코어를 중심으로 ISDNS S/T 인터페이스를 통한 통신망 접속 기능, 톤 발생 및 음성 코덱 기능, TDM 버스 정합 기능, PC 정합 기능을 가지는 ISDN 시스템 칩을 설계 및 개발하였고, 이 칩을 시험하기 위한 시험 프로그램 및 통신 단말 소프트웨어를 개발하였으며, 응용단말을 구현하여 자체 기능 시험 및 실제 망 접속 시험을 통하여 기능을 검증하였다.

• Journal of Information Processing Systems
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• 제5권4호
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• pp.187-196
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• 2009

This paper presents compact cryptographic hardware architecture suitable for the Mobile Trusted Module (MTM) that requires low-area and low-power characteristics. The built-in cryptographic engine in the MTM is one of the most important circuit blocks and contributes to the performance of the whole platform because it is used as the key primitive supporting digital signature, platform integrity and command authentication. Unlike personal computers, mobile platforms have very stringent limitations with respect to available power, physical circuit area, and cost. Therefore special architecture and design methods for a compact cryptographic hardware module are required. The proposed cryptographic hardware has a chip area of 38K gates for RSA and 12.4K gates for unified SHA-1 and SHA-256 respectively on a 0.25um CMOS process. The current consumption of the proposed cryptographic hardware consumes at most 3.96mA for RSA and 2.16mA for SHA computations under the 25MHz.

• IEIE Transactions on Smart Processing and Computing
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• 제5권2호
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• pp.143-151
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• 2016

This paper presents new prediction methods to improve compression performance of the so-called near-lossless RGB-domain image coder, which is designed to effectively decrease the memory bandwidth of a system-on-chip (SoC) for image processing. First, variable block size (VBS)-based intra prediction is employed to eliminate spatial redundancy for the green (G) component of an input image on a pixel-line basis. Second, inter-color prediction (ICP) using spectral correlation is performed to predict the R and B components from the previously reconstructed G-component image. Experimental results show that the proposed algorithm improves coding efficiency by up to 30% compared with an existing algorithm for natural images, and improves coding efficiency with low computational cost by about 50% for computer graphics (CG) images.

• 전자공학회논문지A
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• 제29A권2호
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• pp.100-106
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• 1992

In this pape, we designed and implemented a hardware accelerator for the generation of bit map font from Hangul outline font description for LBP (Laser Beam Printer) and screen applications Whole system was implemented as a double size PC/AT application board which consists of processing bolck and display block. The processing block has a master processor (MC68000)and two slave processors which are MC56001 and KAFOG chip responsible for the short vector generation. In the display block, TMS34061 was used for monitor display and GP425 was used for LBP print out. The resolution of the monitor is 640$\times$480 and that of LBP is 2385$\times$3390. The current system called KHGB90-B generates about 100 characters per second where each character consists of 32$\times$32 bits

• 전자공학회논문지A
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• 제31A권4호
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• pp.127-135
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• 1994

In this paper we propose an EWLD(Enhanced Weighted Levenshtein Distance) algorithm to organize code-string pattern matching linear array processor based on the mappting to an one-dimensional array from a two-dimensional matching matrix, and design a processing element(PE) of the processor, N PEs are required instead of NS02T in the processor because of the mapping. Data input and output between PEs and all internal operations of each PE are performed in bit-serial fashion. The bit-serial operation consists of the computing of word distance (WD) by comparison and the selection of optimal code transformation path, and takes 22 clocks as a cycle. The layout of a PE is designed based on the double metal $1.5\mu$m CMOS rule. About 1,800 transistors consistute a processing element and 2 PEs are integrated on a 3mm$\times$3mm sized chip.

• 한국생물정보학회:학술대회논문집
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• 한국생물정보시스템생물학회 2000년도 International Symposium on Bioinformatics
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• pp.45-52
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• 2000

Genomic approach produces massive amount of data within a short time period, New high-throughput automatic sequencers can generate over a million nucleotide sequence information overnight. A typical DNA chip experiment produces tens of thousands expression information, not to mention the tens of megabyte image files, These data must be handled automatically by computer and stored in electronic database, Thus there is a need for systematic approach of data collection, processing, and analysis. DNA sequence information is translated into amino acid sequence and is analyzed for key motif related to its biological and/or biochemical function. Functional genomics will play a significant role in identifying novel drug targets and diagnostic markers for serious diseases. As an enabling technology for functional genomics, bioinformatics is in great need worldwide, In Korea, a new functional genomics project has been recently launched and it focuses on identi☞ing genes associated with cancers prevalent in Korea, namely gastric and hepatic cancers, This involves gene discovery by high throughput sequencing of cancer cDNA libraries, gene expression profiling by DNA microarray and proteomics, and SNP profiling in Korea patient population, Our bioinformatics team will support all these activities by collecting, processing and analyzing these data.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2000년도 추계학술발표논문집 (상)
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• pp.465-468
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• 2000

본 논문에서는 인식코드를 전송할 수 있는 modulator 뿐만 아니라 Reader system으로부터 코드 전송제어 명령어를 수신할 수 있고 향후 EEPROM과 더불어 인식코드를 수정할 수 있는 RFID (Radio Frequency IDentification) Transponder 칩 설계에 관한 내용을 다룬다. RFID칩은 배터리를 사용하지 않고 명령어와 함께 형성되는 Field로부터 전원을 생성하고 동시에 코드를 제공하는 Full-Duplex 구조로 설계하였다. Transponder IC는 power-generation 회로, clock generation 회로, digital block, modulator, overvoltage protection 회로로 구성된다. 설계된 칩은 저전력 회로를 적용하여 원거리 transponder칩을 구현할 수 있도록 하였다. 설계된 회로는 $0.6{\mu}m$ 현대 CMOS 공정으로 레이아웃 하였으며 제작중에 있다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1990년도 하계학술대회 논문집
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• pp.471-474
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• 1990

In this paper, a vision-based inspection algorithm for checking mark quality on an integrated chip(IC) is proposed. In order to reduce the processing time for inspection, we are implemented image arithmetic unit and binary image projection processor in hardware. By adopting the hardwares, the processing time becomes less one sixth of that in case of using software only.

• 한국방송∙미디어공학회:학술대회논문집
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• 한국방송공학회 1995년도 학술대회
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• pp.165-170
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• 1995

In this paper, it is attempted to apply the adaptive digital signal processing to compensate for a linear distortion of a loudspeaker and implement a real time hardware for that purpose. The real time system is implemented by using the DSP56001, a general purpose signal processor, as a host processor and the DSP56200, a cascadable adaptive FIR filter peripheral chip, as an adaptive digital filter. The system has 1000 taps at a 44.1kHz. After inverse modeling of under_compensation_speaker, the system reduces loudspeaker's linear distortions by pre-processing an input audio signal to loudspeaker. The experiment shows satisfactory results; after adaption with white noise as input signal for 60sec, the flat amplitude and linear phase frequency characteristics is found to lie over a wide frequency range of 100Hz to 20kHz.