• Title/Summary/Keyword: chip processing

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A Study on Worker Risk Reduction Methods using the Deep Learning Image Processing Technique in the Turning Process (선삭공정에서 딥러닝 영상처리 기법을 이용한 작업자 위험 감소 방안 연구)

  • Bae, Yong Hwan;Lee, Young Tae;Kim, Ho-Chan
    • Journal of the Korean Society of Manufacturing Process Engineers
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    • v.20 no.12
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    • pp.1-7
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    • 2021
  • The deep learning image processing technique was used to prevent accidents in lathe work caused by worker negligence. During lathe operation, when the chuck is rotated, it is very dangerous if the operator's hand is near the chuck. However, if the chuck is stopped during operation, it is not dangerous for the operator's hand to be in close proximity to the chuck for workpiece measurement, chip removal or tool change. We used YOLO (You Only Look Once), a deep learning image processing program for object detection and classification. Lathe work images such as hand, chuck rotation and chuck stop are used for learning, object detection and classification. As a result of the experiment, object detection and class classification were performed with a success probability of over 80% at a confidence score 0.5. Thus, we conclude that the artificial intelligence deep learning image processing technique can be effective in preventing incidents resulting from worker negligence in future manufacturing systems.

2D/3D Visual Optical Inspection System for Quad Chip (Quad Chip 외관 불량 검사를 위한 2D/3D 광학 시스템)

  • Han, Chang Ho;Lee, Sangjoon;Park, Chul-Geon;Lee, Ji Yeon;Ryu, Young-Kee;Ko, Kuk Won
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.17 no.1
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    • pp.684-692
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    • 2016
  • In the manufacturing process of the LQFP/TQFP (Low-profile Quad Flat Package/Thin Quad Flat Package), the requirement of a 3 dimensional inspection is increasing rapidly and a 3D inspection of the shape of a chip has become an important report of quality control. This study developed a 3 dimensional measurement system based on PMP (Phase Measuring Profilometry) for an inspection of the LQFP/TQFP chip and image processing algorithms. The defects of the LQFP/TQFP chip were classified according to the dimensions. The 2 dimensional optical system was designed by the dorm illumination to achieve constant light distribution, In the 3 dimensional optical system, PZT was used for moving 90 degree in phase. The problem of 2 ambiguity was solved from the measured moir? pattern using the ambiguity elimination algorithm that finds the point of ambiguity and refines the phase value. The proposed 3D measurement system was evaluated experimentally.

Improvement of KOMPSAT Imagery Locational Accuracy Using Value-Added Processing System (부가처리시스템을 이용한 다목적실용위성 영상자료 위치정확도 개선)

  • LEE, Kwang-Jae;YUN, Hee-Cheon;KIM, Youn-Soo
    • Journal of the Korean Association of Geographic Information Studies
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    • v.18 no.4
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    • pp.68-80
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    • 2015
  • To increase the utilization of the KOrea Multi-Purpose SATellite(KOMPSAT) series imagery being developed pursuant to the national space development program, high quality images with enhanced locational accuracy should be created through standardized post-processing processes. In the present study, using the Value-Added Processing System(VAPS) constructed for the post-processing of KOMPSAT imagery, location correction experiments were conducted using KOMPSAT-2 and -3 imagery from domestic and overseas regions. First, 50 pieces from each of KOMPSAT-2 imagery were selected from South Korean and North Korean regions, and modeling was conducted using GCP Chips. According to the results, the Root Mean Square Errors(RMSE) for South Korea and North Korea were 1.59 pixels and 2.04 pixels, respectively, and the locational accuracy of ortho mosaic imagery using check points were 1.33m(RMSE) and 1.90m(RMSE), respectively. Meanwhile, in the case of overseas regions for which GCP could not be easily obtained, the improvement of locational accuracy could be identified through image corrections using Open Street Map(OSM). The VAPS and reference materials used in the present study are expected to be very useful in constructing a precise image DB for entire global regions.

Architecture design for speeding up Multi-Access Memory System(MAMS) (Multi-Access Memory System(MAMS)의 속도 향상을 위한 아키텍처 설계)

  • Ko, Kyung-sik;Kim, Jae Hee;Lee, S-Ra-El;Park, Jong Won
    • Journal of the Institute of Electronics and Information Engineers
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    • v.54 no.6
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    • pp.55-64
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    • 2017
  • High-capacity, high-definition image applications need to process considerable amounts of data at high speed. Accordingly, users of these applications demand a high-speed parallel execution system. To increase the speed of a parallel execution system, Park (2004) proposed a technique, called MAMS (Multi-Access Memory System), to access data in several execution units without the conflict of parallel processing memories. Since then, many studies on MAMS have been conducted, furthering the technique to MAMS-PP16 and MAMS-PP64, among others. As a memory architecture for parallel processing, MAMS must be constructed in one chip; therefore, a method to achieve the identical functionality as the existing MAMS while minimizing the architecture needs to be studied. This study proposes a method of miniaturizing the MAMS architecture in which the architectures of the ACR (Address Calculation and Routing) circuit and MMS (Memory Module Selection) circuit, which deliver data in memories to parallel execution units (PEs), do not use the MMS circuit, but are constructed as one shift and conditional statements whose number is the same as that of memory modules inside the ACR circuit. To verify the performance of the realized architecture, the study conducted the processing time of the proposed MAMS-PP64 through an image correlation test, the results of which demonstrated that the ratio of the image correlation from the proposed architecture was improved by 1.05 on average.

Optimization of Cooling Conditions by Supplying Cutting Oil Applied with Mist Nozzle to Minimize Tapping Processing Temperature (Tapping 가공 온도 최소화를 위해 미스트 노즐 적용 절삭유 공급에 따른 냉각조건 최적화)

  • Oh, Chang-hyouk;Kim, Young-Shin;Jeon, Euy-Sik
    • Journal of the Korean Society of Manufacturing Process Engineers
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    • v.21 no.5
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    • pp.98-104
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    • 2022
  • When processing parts, the cutting oil can improve the cooling performance of the workpiece and tool to increase the precision of the workpiece or extend the life of the tool and facilitate chip extraction. Since such cutting oil has a harmful effect on the environment and the human body due to additives such as sulfur, research on a minimum lubrication supply method using an eco-friendly oil is recently underway. The minimum lubrication supply method minimizes the amount of cutting oil used during processing and processes it, which can reduce the amount of cutting oil used, but has a problem in that cooling performance efficiency is poor. Therefore, this study conducted a study on mist cooling of lubricants to reduce the amount of cutting oil used and maximize the cooling effect of processing heat generated during tapping processing. Spray pressure, processing speed, direction, and lubricant spray amount, which are considered to have an effect on cooling performance, were set as process conditions, and the effect on temperature was analyzed by performing an experiment using the box benquin method among experiments were analyzed. Through the experimental analysis results, the optimal conditions for mist and processing that maximize the cooling effect were derived, and the validity of the results derived through additional experiments was verified. In the case of processing by applying the mist lubrication method verified through this study, it is considered that high-precision processing is possible by improving the cooling effect.

The Study on Method of Register Setting for Using CC1020 Chip (CC1020 동작을 위한 레지스터 설정방법에 대한 연구)

  • Lim, Hyun-Jin;Jo, Heung-Kuk
    • Proceedings of the Korea Institute of Convergence Signal Processing
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    • 2005.11a
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    • pp.347-352
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    • 2005
  • 유비쿼터스라는 새로움 페러다임의 도래로 인해 많은 IT산업이 이를 중심으로 많은 발전을 하고 있다. 이러한 유비쿼터스 관련 산업에 있어서 상당 부분 무선 통신기술인 RF를 기반으로 하고 있으며, 이를 활용하여 RFID 시스템 및 센서 네트워크 등이 발전하고 있는 추세이다. 본 논문에서 이러한 무선 통신기술에 적합한 저전력 저전압 Wireless UHF 트렌시버인 CC1020 칩을 이용하여 무선통신시스템을 구현하였다. 이 시스템을 제어하기 위해 MCU와의 Interface를 구성하고 CC1020 칩의 레지스터를 설정하기 위해 4선의 직렬 구성 인터페이스로 모토로라사에서 개발된 근거리용 고속 직렬 동기식 통신규격인 SPI 방식을 이용하였다. 따라서 레지스터 종류 및 설정순서와 타이밍에 대한 내용과 MCU와의 인터페이스 중심으로 설명하였으며, 시스템을 구현하고 실험을 통해 신호의 파형과 데이터 송수신을 확인하였다.

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High Throughput Parallel Decoding Method for H.264/AVC CAVLC

  • Yeo, Dong-Hoon;Shin, Hyun-Chul
    • ETRI Journal
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    • v.31 no.5
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    • pp.510-517
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    • 2009
  • A high throughput parallel decoding method is developed for context-based adaptive variable length codes. In this paper, several new design ideas are devised and implemented for scalable parallel processing, a reduction in area, and a reduction in power requirements. First, simplified logical operations instead of memory lookups are used for parallel processing. Second, the codes are grouped based on their lengths for efficient logical operation. Third, up to M bits of the input stream can be analyzed simultaneously. For comparison, we designed a logical-operation-based parallel decoder for M=8 and a conventional parallel decoder. High-speed parallel decoding becomes possible with our method. In addition, for similar decoding rates (1.57 codes/cycle for M=8), our new approach uses 46% less chip area than the conventional method.

Field programmable analog arrays for implementation of generalized nth-order operational transconductance amplifier-C elliptic filters

  • Diab, Maha S.;Mahmoud, Soliman A.
    • ETRI Journal
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    • v.42 no.4
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    • pp.534-548
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    • 2020
  • This study presents a new architecture for a field programmable analog array (FPAA) for use in low-frequency applications, and a generalized circuit realization method for the implementation of nth-order elliptic filters. The proposed designs of both the FPAA and elliptic filters are based on the operational transconductance amplifier (OTA) used in implementing OTA-C filters for biopotential signal processing. The proposed FPAA architecture has a flexible, expandable structure with direct connections between configurable analog blocks (CABs) that eliminates the use of switches. The generalized elliptic filter circuit realization provides a simplified, direct synthetic method for an OTA-C symmetric balanced structure for even/odd-nth-order low-pass filters (LPFs) and notch filters with minimum number of components, using grounded capacitors. The filters are mapped on the FPAA, and both architectures are validated with simulations in LTspice using 90-nm complementary metal-oxide semiconductor (CMOS) technology. Both proposed FPAA and filters generalized synthetic method achieve simple, flexible, low-power designs for implementation of biopotential signal processing systems.

Rheological perspectives of industrial coating process

  • Kim, Sun-Hyung;Kim, Jae-Hong;Ahn, Kyung-Hyun;Lee, Seung-Jong
    • Korea-Australia Rheology Journal
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    • v.21 no.2
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    • pp.83-89
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    • 2009
  • Coating process plays an important role in information technology such as display, battery, chip manufacturing and so on. However, due to complexity of coating material and fast deformation of the coating flow, the process is hard to control and it is difficult to maintain the desired quality of the products. Moreover, it is hard to measure the coating process because of severe processing conditions such as high drying temperature, high deformation coating flow, and sensitivity to the processing variables etc. In this article, the coating process is to be re-illuminated from the rheological perspectives. The practical approach to analyze and quantify the coating process is discussed with respect to coating materials, coating flow and drying process. The ideas on the rheology control of coating materials, pressure and wet thickness control in patch coating process, and stress measurement during drying process will be discussed.

Implementation and evaluation of stereo audio codec using perceptual coding (지각 부호화를 이용한 스테레요 오디오 코덱의 구현 및 음질 평가)

  • 차경환;장대영;홍진우;김천덕
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.33B no.4
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    • pp.156-163
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    • 1996
  • In this paper, we described the implementation and the sound quality assessment of a real-time stereo audio codec using TMS320C40 DSP (digital signal processing) chip for low bitrte and high quality audio. We implemented hardware and software in order to overcome a real-time processing problem of audio compression algorithm that can be produced by largely recursive computing and complexity of the process. We have studied five types of distortion that can be produced by perceptual coding and the codec was evaluated by eight test musics that are selected in SQAM (sound quality assessment material) 422-2-4-2 produced by EBU (european broadcast union). The subjective listening tests were carried out on the codec quality and preformance by double blind method in a listening room with eleven listeners. As a result, 5 grade-impairment scale was scored under minus one and the codec quality was evaluated to be perceptible, but not annoying.

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