• The Transactions of the Korea Information Processing Society
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• v.2 no.1
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• pp.66-74
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• 1995

A 8-bit 15MHz CMOS subranging Analog-to-Digital converter for high-speed, low-power consumption applications is described. Subranging, 2 step flash, A/D converter used a new resistor string and a simple comparator architecture for the low power consumption and small chip area. Comparator exhibites 80dB loop gain, 50MHz conversion speed, 0.5mV offset and maximum error of voltage divider was 1mV. This Analog-to-Digital converter has been designed and fabricated in 1.2 m N-well CMOS technology. It consumed 150mW power at ＋5/-5V supply and delayed 65ns. The proposed Analog-to-Digital converter seems suitable for high- speed, low-power consumption, small area applications and one-chip mixed Analog- Digital system. Simulations are performed with PSPICE and a fabricated chip is tested.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.131-139
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• 2013

To overcome the limitations in performance and power consumption of traditional electrical interconnection based network-on-chips (NoCs), a hybrid optical network-on-chip (HONoC) architecture using optical interconnects is emerging. However, the HONoC architecture should use circuit-switching scheme owing to the overhead by optical devices, which worsens the latency unfairness problem caused by frequent path collisions. This resultingly exert a bad influence in overall performance of the system. In this paper, we propose a new task mapping algorithm for optimizing latency by reducing path collisions. The proposed algorithm allocates a task to a certain processing element (PE) for the purpose of minimizing path collisions and worst case latencies. Compared to the random mapping technique and the bandwidth-constrained mapping technique, simulation results show the reduction in latency by 43% and 61% in average for each $4{\times}4$ and $8{\times}8$ mesh topology, respectively.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.2
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• pp.11-19
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• 2015

Since CMOS device scaling has stalled, three-dimensional (3-D) integration allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. 3-D integration has many benefits such as increased multi-functionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, because it vertically stacks multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip. Anticipated applications start with memory, handheld devices, and high-performance computers and especially extend to multifunctional convengence systems such as cloud networking for internet of things, exascale computing for big data server, electrical vehicle system for future automotive, radioactivity safety system, energy harvesting system and, wireless implantable medical system by flexible heterogeneous integrations involving CMOS, MEMS, sensors and photonic circuits. However, heterogeneous integration of different functional devices has many technical challenges owing to various types of size, thickness, and substrate of different functional devices, because they were fabricated by different technologies. This paper describes new 3-D heterogeneous integration technologies of chip self-assembling stacking and 3-D heterogeneous opto-electronics integration, backside TSV fabrication developed by Tohoku University for multifunctional convergence systems. The paper introduce a high speed sensing, highly parallel processing image sensor system comprising a 3-D stacked image sensor with extremely fast signal sensing and processing speed and a 3-D stacked microprocessor with a self-test and self-repair function for autonomous driving assist fabricated by 3-D heterogeneous integration technologies.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.9
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• pp.1115-1124
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• 1988

A two-dimensional systolic array for fast Fourier transform, which has a regular and recursive VLSI architecture is presented. The array is constructed with identical processing elements (PE) in mesh type, and due to its modularity, it can be expanded to an arbitrary size. A processing element consists of two data routing units, a butterfly arithmetic unit and a simple control unit. The array computes FFT through three procedures` I/O pipelining, data shuffling and butterfly arithmetic. By utilizing parallelism, pipelining and local communication geometry during data movement, the two-dimensional systolic array eliminates global and irregular commutation problems, which have been a limiting factor in VLSI implementation of FFT processor. The systolic array executes a half butterfly arithmetic based on a distributed arithmetic that can carry out multiplication with only adders. Also, the systolic array provides 100% PE activity, i.e., none of the PEs are idle at any time. A chip for half butterfly arithmetic, which consists of two BLC adders and registers, has been fabricated using a 3-um single metal P-well CMOS technology. With the half butterfly arithmetic execution time of about 500 ns which has been obtained b critical path delay simulation, totla FFT execution time for 1024 points is estimated about 16.6 us at clock frequency of 20MHz. A one-PE chip expnsible to anly size of array is being fabricated using a 2-um, double metal, P-well CMOS process. The chip was layouted using standard cell library and macrocell of BLC adder with the aid of auto-routing software. It consists of around 6000 transistors and 68 I/O pads on 3.4x2.8mm\ulcornerarea. A built-i self-testing circuit, BILBO (Built-In Logic Block Observation), was employed at the expense of 3% hardware overhead.

• Journal of the Institute of Convergence Signal Processing
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• v.5 no.4
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• pp.333-337
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• 2004

This paper describe a design of 5GHz OFDM baseband chip for IEEE 802.11a wireless LAN. The proposed device is consists of transmitter and receiver within a single FPGA chip. We applied single tap equalizer that use Normalized LMS algorithm to remove ISI that happen at high speed data transmission. And also, we used carrier wave frequency offset algorithm that use training symbol to remove ICI. The simulation results show the correct transmission without errors the between transmitter and receiver And we can remarkably reduce the number of register through the synthesized circuits by using DSP block and EMB(Embedded Memory Block). The target device for implementation of the synthesized circuits is Altera Stratix EPIS25FC672 FPGA and design platform is VHDL.

• Journal of the Microelectronics and Packaging Society
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• v.9 no.4
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• pp.47-53
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• 2002

In this study, two different (NiCuZn)-ferrite which were fabricated by using ultra-fine powders synthesized by the wet processing and conventionally commercialized powder, were investigated and compared each other in terms of the low temperature sintering and electromagnetic properties. Composition of x and w in $(Ni_{0.4-x}Cu_xZn_{0.6})_{1+w}(Fe_2O_4)_{1-w}$ were controlled as 0.2 and 0.03, respectively. The sintering temperature were $900^{\circ}C$ for ultra-fine powders by way of initial heat treatment and $1150^{\circ}C$ for commercialized powders. The (NiCuZn)-ferrite by ultra-fine powders showed love. sintering temperature than that of commercialized powders by over $200^{\circ}C$, and excellent electromagnetic properties such as the quality factor which is a important factor in the multi-layered chip inductor. In addition, characteristics of B-H hysteresis, crystallinity, microstructure and powder morphology were analyzed by a vibrating sample method(VSM), x-ray diffractometer(XRD), transmission electron microscope (TEM) and scanning electron microscope(SEM).

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.1
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• pp.159-164
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• 2013

Recently the solution integrated of vision and motion controller which are important element in automatiomn system has been many developed. However typically such a solutions has a many case that integrated vision processing and motion control into network or organized two chip solution on one module. We implement one chip solution integrated into vision and motion controller using Zynq-7000 that is developed recently as extended processing platform. We also apply EtherCAT to motion control that is industrial Ethernet protocol which have compatibility for open standardization Ethernet in order to control of motion because EtherCAT has a secure to realtime control and can treat massive data.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.193-202
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• 2012

In this paper, we propose a new approach for compact range sensor system for real-time robot applications. Instead of using off-the-shelf camera and projector, we devise a compact system with a CMOS image-sensor and a DMD (Digital Micro-mirror Device) that yields smaller dimension ($168{\times}50{\times}60mm$) and lighter weight (500g). We also realize one chip hard-wired processing of projection of structured-light and computing the range by exploiting correspondences between CMOS images-ensor and DMD. This application-specific chip processing is implemented on an FPGA in real-time. Our range acquisition system performs 30 times faster than the same implementation in software. We also devise an efficient methodology to identify a proper light intensity to enhance the quality of range sensor and minimize the decoding error. Our experimental results show that the total-error is reduced by 16% compared to the average case.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.11
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• pp.1-7
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• 2004

We propose multistage parallel nulling (MPN) partial parallel interference cancellation (PPIC) receiver for downlink multiple-input multiple-output (MIMO) multicarrier (MC)-code division multiple access (CDMA) systems. Though the V-BLAST is a popular MIMO receiver, it shows error floor for multiuser downlink MIMO MC-CDMA systems. The proposed MPN-PPIC receiver does not produce error floor for multiuser case, and achieves substantial performance gains with multistage processing. For single user case, the proposed method also surpasses the V-BLAST receiver with multistage processing for MIMO MC-CDMA systems with chip level interleaving. The system performance of the proposed MPN-PPIC receiver is evaluated through computer simulations.

• The Transactions of the Korea Information Processing Society
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• v.4 no.6
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• pp.1565-1575
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• 1997

A new encryption algorithm had been proposed as a replacement to the Data Encryption Standard (DES) in [1,2]. It called the Extended DES (EDES) has a key length of 112 bits. The plaintext data consists of 96 bits divided into 3 sub-blocks of 32 bits each. The EDES has a potentially higher resistance to differential cryptanalysis that the DES due to the asymmetric number of f functions performed on each of the 3 sub-blocks and due to the increase of S-boxes from 8 to 16. This paper propose a hardware design for the EDES and its implementation in VLSI. The VLSI chip implements data encryption and decryption in a single hardware unit. With a system clock frequency of 15Mhz the device permits a data conversion rate of about 90Mbit/sec. Therefore, the chip can be applied to on-line encryption in high-speed networking protocols.