• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.2
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• pp.431-436
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• 2009

Home network is a rapidly growing area as new technologies are emerging, and new applications are being developed. The progress of home network technologies is growing the home network management technology for control and management of the digital appliances. Embodiment of these home network show marked ich have use for complicated and diversifiable processing. Design of home network system does very important stage through home network comes essential pars. In this paper, We designed and constitute Home network system which designs module using embedded system, STR710F Chip and CC2420 RF Module-Chip with the intention for using RS232C and USB.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2003.10a
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• pp.334-343
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• 2003

The discharge gap clearly is to order and to promote the improvement of processing feature of die-sinking electro discharge machining(EDM). If creation carbon, which generated by Pyrolysis of EDM oil and processing pace power which is generated in between an electrode and a workpiece, are overproduced, they will lower the processing speed and roughness of the surface. Therefore, it is gone through an experiment and the flow analysis of EDM oil in order to improve the treatment of processing chips, which is an important problem by contriving a new flushing method. The condition of an electric discharge is not considered to be a progressing of processing. It is assumed that the flow of processing fluid is equal to the flow of processing chip, which is remaining in the discharge gap, and thus, analyzing then comparing with the data of the experiment and investigate its correlation.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2005.05a
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• pp.272-277
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• 2005

The discharge gap clearly is to order and to promote the improvement of processing feature of die-sinking electro discharge machining(EDM). If creation carbon, which generated by pyrolysis of EDM oil and processing pace power which is generated in between an electrode and a workpiece, are overproduced, they will lower the processing speed and roughness of the surface. Therefore, it is gone through the .flow analysis of EDM oil in order to improve the treatment of processing chips, which is an important problem by contriving a new flushing method. The condition of an electric discharge is not considered to be a progressing of processing. It is assumed that the flow of processing fluid is equal to the flow of processing chip, which is remaining in the discharge gap, and analyzing its correlation.

• Korean Journal of Plant Resources
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• v.16 no.3
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• pp.264-274
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• 2003

Many potato genetic resources have been collected and improved for their diverse traits over the years using breeding program in KPGR. To select potential varieties for table and processing in Korea, 58 elite potato breeding lines and several 'Valley' varieties were cultivated and harvested at Korea Alpine area in 2001. The cultivated lines and varieties were evaluated using their cultural adaptability in the environment and tuber characteristics, such as the depth of tuber eye, tuber shape, skin color, flesh color, scab resistance, yield, and the resistance of hollow heart and internal brown spot disease. Additionally, in the selection of potential processing varieties, reducing sugar content (sum of glucose and fructose concentration) of tubers is critically considered, because it mainly influence on the chip color of processing potato tuber. For table stock varieties with white skin color, 'Early Valley', 'Summer Valley', 'Winter Valley', and 'Taebok Valley' were selected. In the aspect of diverse potato tuber color, several varieties were selected such as 'Golden Valley' for its yellow fresh and skin color, 'Gogu Valley', 'Juice Valley', and 'Rose Valley' for their red skin color, and 'Purple Valley' for its purple skin. Compared with world wide known processing cultivar 'Atlantic', 24 lines (or varieties) were selected for the potential potato processing industry due to their low reducing sugar contents (below 0.3％), high yield (above 4.0 ton/ha), and unique chip colors. Selected white chipping varieties were 'Taedong Valley', 'Kangshim Valley', and 'Kangwon Valley', which have 0.23％, 0.27％, and 0.29％ of reducing sugar contents, respectively. 'Bora Valley', having deep purple color in both skin and fresh, was selected for purple chip variety and has 0.26％ of reducing sugar content. Light yellow chip varieties (lines) were 'Rose Valley' and Valley 54, having 0.19％ and 0.269％ of reducing sugar content, respectively. For French frying potatoes, 'Stick Valley' of 0.22％ and Valley 72 of 0.151％ in reducing sugars were selected. All of these selected lines and 'Valley' varieties can be used as parents to improve potato genetic resources and to develop better varieties with unique traits and colors.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.2
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• pp.505-516
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• 2000

Cellular Neural Networks(CNN) is a nonlinear information-processing system that has a locally connected characteristic and is widely used in the real-time high speed image processing. In this paper, a practical system approach of time-multiplexing CNN implementations suitable for processing large and complex images using small CNN arrays is presented and $6\times6$ CNN hardware is designed for the processing of a large image. While previous implementations are mostly suitable for black and white applications because of the thresholded outputs, our approach is especially suitable for applications in gray image processing due to the analog nature of the state node. CNN chip is designed using a 0.65${\mu}{\textrm}{m}$ 2P2M(double poly, double metal) N-Well CMOS process technology. It contains about 15,400 devices on an area of about $1.85\times1.75$ md. The designed $6\times6$ CNN is tested for the edge detection of a large image input and it's performance is verified.

• Journal of Korea Multimedia Society
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• v.2 no.4
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• pp.367-377
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• 1999

Nowadays, the number of database applications which need fast transaction processing are increasing. One way to improve the performance of transaction processing is to reside the whole database in main memory As semiconductor memory becomes cheaper and chip densities increase, the research to improve transaction throughput rates of transaction processing system, using main memory databases, has begun In this thesis, how to implement a high performance transaction processing system based on main memory databases, new concurrency control scheme, recovery scheme and storage structure is presented. The objective of the proposed schemes is to improve the transaction processing system performance measured by transaction throughput and response times.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.4
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• pp.618-624
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• 1987

This paper describes the design and fabrication of a signal processing integrated circuit required for the recording and playback of VTR audio signal. The integrated circuit was designed using 8\ulcorner design rule and its chip size is 2.5x2.5mm\ulcorner It was fabricated using SST bipolar standard process technology. The measurement analysis of the fabricated circuit proves the satisfactory DC characteristics and its proper audio signal processing funcstion.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.2
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• pp.119-124
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• 1988

Real-time adaptive lattice predictor was implemented on the TMS32020 DSP chip for digital signal processing. The implemented system was composed of Input-Output units and centrla processing-control unit and its supporting assembly soft ware. The performance of hardware realization was verified by comparing input signal and one-step prediction signal which are calcualted by the real-time adaptive lattice predictor. As a result, for 4 stage lattice structure, the maximum running frequency was obtained as 6.41 KHz in this experiment.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2003.06a
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• pp.197-200
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• 2003

본 논문에서는 IEEE 802.11a 무선 LAN 용 CODEC 회로를 설계하고, VHDL 코딩과 FPGA에 의한 회로설계 검증에 관해 기술한다. IEEE 802.lla WLAN CODEC의 구조는 크게 데이터 보호를 위한 스크램블러/디스크램블러, 채널 에러에 대한 정보보호를 위한 Convolutional 부호기와 Viterbi 복호기로 구성된 채널 코덱, 그리고 연집에러를 랜덤 에러로 변화시키는 인터리버/디인터리버로 구성된다. 본 논문에서는, 이와 같은 CODEC의 각 부분을 하드웨어로 구현하기 위한 새로운 회로구성을 제안하고, 그 성능을 VHDL 코딩에 의한 시뮬레이션과 FPGA에 의한 하드웨어 검증 결과를 제시한다.

• Proceedings of the Korea Information Processing Society Conference
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• 2009.04a
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• pp.7-10
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• 2009

본 연구에서는 차량 네트워크를 구성하는 CAN(Controller Area Network), MOST(Media Oriented System Transport)등의 버스 시스템을 중심으로 IVN(In-Vechicle Network)에 대한 선행연구와 지능형 통합 Gateway 개발 연구를 통해 통합적인 차량 상태정보 수집 및 교환을 위한 차량 Gateway를 제시하고, Soc(System on Chip)형태의 차량용 인터페이스(HMI, Human Machine Interface)를 통한 지능형 통합 GateWay 통신 기술을 OSGi의 번들 형태로 제작하여 알아본다.