• Journal of the Korean Society for Nondestructive Testing
• /
• v.12 no.4
• /
• pp.18-25
• /
• 1993

This paper is to aim the microdefect evaluation of If package into a quantitative from NDI's image processing of ultrasonic wave. (1) Automatically repeated discrimination analysis method can be devided in the category of all kind of defects on IC package, and also can be possible to have a sampling of partial delamination. (2) It is possible that the information of edge section in silicon chip surrounding can be extractor by the partial image processing of IC package. Also, the crack detection is possible between the resin part and lead frame.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2015.05a
• /
• pp.381-382
• /
• 2015

Small devices such as MLCC, sample inspection on the processing is not easy. If you can proceed with the sample inspection, the production process will be able to maximize the MLCC production efficiency. In this study, to minimize the interference of operator, and to maximize the operating efficiency of the equipment. Use image processing techniques for its extracts the position and angle of the MLCC. Implements an automatic inspection system with the high productivity.It is possible to inspect the final six MLCC devices. And once we Pick-Up to 200 Chip to check the accuracy of 98.4%. Based on the results of various studies are in progress to be expected to be applicable to the automatic inspection equipment side development of a variety of small devices.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.2
• /
• pp.28-34
• /
• 2011

In this paper, we present integer and fractional motion estimation IP for H.264/AVC encoder by hardware-oriented algorithm. In integer motion engine, the reference block is used to share for consecutive current macro blocks in parallel processing which exploits data reusability and reduces off-chip bandwidth. In fractional motion engine, instead of two-step sequential refinement, half and quarter pel are processed in parallel manner in order to discard unnecessary candidate positions and double throughput. The H.264/AVC motion estimation chip is fabricated on a MPW(Multi-Project Wafer) chip using the chartered $0.18{\mu}m$ standard CMOS 1P5M technology and achieves high throughput supporting HDTV 720p 30 fps.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.10 no.4
• /
• pp.288-294
• /
• 2017

Recently, deep learning using convolutional neural network (CNN) has been extensively studied in image recognition. Convolution consists of addition and multiplication. Multiplication is computationally expensive in hardware implementation, relative to addition. It is also important factor limiting a chip design in an embedded deep learning system. In this paper, I propose a parallel-addition processing algorithm that converts grayscale images to the superposition of binary images and performs convolution only with addition. It is confirmed that the convolution can be performed by a parallel-addition method capable of reducing the processing time in experiment for verifying the availability of proposed algorithm.

• The KIPS Transactions:PartA
• /
• v.8A no.2
• /
• pp.147-156
• /
• 2001

A high performance routing switch is an essential device to either the high performance parallel processing or communication networks that handle multimedia transfer systems such as VOD. The high performance routing chip called STC104 is a typical example in the technical aspect which has 32 bidirectional links of 100Mbps transfer sped. It has exploited new technologies, such as wormhole routing, interval labeling, and adaptive routing method. The high speed router has been applied into some parallel processing system as a single chip. However, its performance over the various interconnection networks with multiple routing chips has not been studied. In this paper, the strucrtures and characteristics of the STC104 have been investigated in order to evaluate the high speed router. Various topology of the STC104, such as meshes, torus, and N-cube are defined and constructed. Algorithms of packet transmission have been proposed based on the interval labeling and the group adaptive routing method implemented in the interconnected network. Multicast algorithms, which are often requited to the processor networks and broadcasting systems, modified from U-mesh and U-torus algorithms have also been proposed overcoming the problems of point-to-point communication.

• The KIPS Transactions:PartD
• /
• v.17D no.3
• /
• pp.175-184
• /
• 2010

Experiments and research on genes have become very convenient by using DNA chips, which provide large amounts of data from various experiments. The data provided by the DNA chips could be represented as a two dimensional matrix, in which one axis represents genes and the other represents samples. By performing an efficient and good quality clustering on such data, the classification work which follows could be more efficient and accurate. In this paper, we use a bio-inspired algorithm called the Particle Swarm Optimization algorithm to propose an efficient clustering mechanism for large amounts of DNA chip data, and show through experimental results that the clustering technique using the PSO algorithm provides a faster yet good quality result compared with other existing clustering solutions.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.26 no.4
• /
• pp.120-126
• /
• 1989

IC chip layout pattern recognition algorithms using image processing techniques are being developed for the automation of manufacturing and inspecting chips. Recognitioin of chip pattern requires feature extraction from nach rrame of chip image adn needs to match the feature data through all frames. In this paper, vertex position and form having layout information are extracted by the feature straightening algorithm, and global coordinates of layout pattern are extracted by the feature straightening algorithm, and global coordinates of layout pattern are obtainnd by vertex form matching from the overlapped area of neighbour frame.

• Journal of the Korean Institute of Intelligent Systems
• /
• v.16 no.5
• /
• pp.556-561
• /
• 2006

It is very important to classify the DNA Chip image pattern in order to acquire useful information about genetic disease of people. In this paper, we developed the novel pattern classification method of DNA Chip image using MLP based back-propagation and Self organizing Map learning algorithm. And then we compared and analyzed these classified pattern results. Also we carried out experiment in the MV2440 board using CPU Cote for S3C2440(ARM 920T) and PC environment, and displayed its results in order to give the genetic information to user mote easily in various environment.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.11 no.2
• /
• pp.3-12
• /
• 2001

Currently, the superscalar architecture dominates todays microprocessor marketplase. As, more transistors are integrated onto larger die, however, an on-chip multiprocessor is regarded as a promising alternative to the superscalar microprocessor. This paper examines the behavior of the next generation block encryption algorithms RC6 and Rijndael on the on-chip multiprocessing microprocessor. Based on the simulation results by using a program-driven simulator, the on-chip multiprocessor can exploit thread level parallelism effectively and overcome the limitation of instruction level parallelism in the next generation block encryption algorithms.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.22 no.6
• /
• pp.43-49
• /
• 2022

FMCW(Frequency Modulated Continuous Wave) Radar is very useful for vehicle collision warning system and autonomous driving sensor. In this paper, the design and implementation of FMCW radar based on two chip MMIC developed as an autonomous driving sensor was described. Especially, generation of frame-based and chirp-based waveform generation and signal processing are mixed to have the strength of maximum detection speed and compensation of speed. This implemented system was analyzed for performance and commercialization potential through lab. test and driving test in K-city.