• BioChip Journal
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• v.12 no.4
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• pp.280-286
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• 2018

Hydrogel scaffolds composed of multiple components are promising platform in tissue engineering as a transplantation materials or artificial organs. Here, we present a new fabrication method for implementing multi-layered macroscopic hydrogel scaffold composed of multiple components by controlling height of hydrogel layer through precise control of ultraviolet (UV) energy density. Through the repetition of the photolithography process with energy control, we can form several layers of hydrogel with different height. We characterized UV energy-dependent profiles with single-layered PEGDA posts photocrosslinked by the modular methodology and examined the optical effect on the fabrication of multi-layered, macroscopic hydrogel structure. Finally, we successfully demonstrated the potential applicability of our approach by fabricating various macroscopic hydrogel constructs composed of multiple hydrogel layers.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.2
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• pp.11-19
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• 2015

Since CMOS device scaling has stalled, three-dimensional (3-D) integration allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. 3-D integration has many benefits such as increased multi-functionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, because it vertically stacks multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip. Anticipated applications start with memory, handheld devices, and high-performance computers and especially extend to multifunctional convengence systems such as cloud networking for internet of things, exascale computing for big data server, electrical vehicle system for future automotive, radioactivity safety system, energy harvesting system and, wireless implantable medical system by flexible heterogeneous integrations involving CMOS, MEMS, sensors and photonic circuits. However, heterogeneous integration of different functional devices has many technical challenges owing to various types of size, thickness, and substrate of different functional devices, because they were fabricated by different technologies. This paper describes new 3-D heterogeneous integration technologies of chip self-assembling stacking and 3-D heterogeneous opto-electronics integration, backside TSV fabrication developed by Tohoku University for multifunctional convergence systems. The paper introduce a high speed sensing, highly parallel processing image sensor system comprising a 3-D stacked image sensor with extremely fast signal sensing and processing speed and a 3-D stacked microprocessor with a self-test and self-repair function for autonomous driving assist fabricated by 3-D heterogeneous integration technologies.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.2
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• pp.11-19
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• 2009

Thermo-mechanical behaviors of wire-bond plastic ball grid array (WB-PBGA) package assemblies are characterized by high-sensitivity moire interferometry. Using the real-time moire setup, fringe patterns are recorded and analyzed for several temperatures. Experiments are conducted for three types of WB-PBGA package that have full grid pattern and perimeter pattern with/without central connections. Bending deformations of the assemblies and average strains of the solder balls are investigated, with an emphasis on the effect of solder interconnection grid patterns, Thermal strain distributions and the location of the critical solder ball in package assemblies are quite different with the form of solder ball grid pattern. For the WB-PBGA-PC, The largest of effective strain occurred in the inner solder ball of perimeter closest to the chip solder balls. The critical solder ball is located at the edge of the chip for the WB-PBGA-FG, at the most outer solder ball of central connections for the WB-PBGA-P/C, and at the inner solder ball closest to the chip for the WB-PBGA-P.

• Korean Journal of Metals and Materials
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• v.48 no.7
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• pp.667-673
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• 2010

Copper filling into TSV (through-silicon-via) and reduction of the filling time for the three dimensional chip stacking were investigated in this study. A Si wafer with straight vias - $30\;{\mu}m$ in diameter and $60\;{\mu}m$ in depth with $200\;{\mu}m$ pitch - where the vias were drilled by DRIE (Deep Reactive Ion Etching) process, was prepared as a substrate. $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. In order to reduce the time required complete the Cu filling into the TSV, the PPR (periodic pulse reverse) wave current was applied to the cathode of a Si chip during electroplating, and the PR (pulse-reverse) wave current was also applied for a comparison. The experimental results showed 100% filling rate into the TSV in one hour was achieved by the PPR electroplating process. At the interface between the Cu filling and Ti/ Au functional layers, no defect, such as a void, was found. Meanwhile, the electroplating by the PR current showed maximum 43% filling ratio into the TSV in an hour. The applied PPR wave form was confirmed to be effective to fill the TSV in a short time.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.4
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• pp.149-154
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• 2018

This paper describes the fabrication and heat transfer property of 50 watts rated LED array module where multiple chips are mounted on chip-on-board type ceramic-metal hybrid substrate with high heat dissipation property for high power street and anti-explosive lighting system. The high heat transfer ceramic-metal hybrid substrate was fabricated by conformal coating of thick film glass-ceramic and silver pastes to form insulation and conductor layers, using thick film screen printing method on top of the high thermal conductivity aluminum alloy heat-spreading panel, then co-fired at $515^{\circ}C$. A comparative LED array module with the same configuration using epoxy resin based FR-4 PCB with thermalvia type was also fabricated, then the thermal properties were measured with multichannel temperature sensors and thermal resistance measuring system. As a result, the thermal resistance of the ceramic-metal hybrid substrate in the $4{\times}9$ type LEDs array module exhibited about one third to the value as that of FR-4 substrate, implying that at least triple performance of heat transfer property as that of FR-4 substrate was realized.

• Journal of the Microelectronics and Packaging Society
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• v.26 no.1
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• pp.29-33
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• 2019

With shrinking form factor and improving performance of electronic packages, high input/output (I/O) density is considered as an important factor. Fan out wafer-level packaging (FO-WLP) has been paid great attention as an alternative. However, FO-WLP is vulnerable to warpage during its manufacturing process. Minimizing warpage is essential for controlling production yield, and in turn, package reliability. While many studies investigated the effect of process and design parameters on warpage using finite element analysis, they did not take uncertainty into consideration. As parameters, including material properties, chip positions, have uncertainty from the point of manufacturing view, the uncertainty should be considered to reduce the gap between the results from the field and the finite element analysis. This paper focuses on the effect of uncertainty of Young's modulus of chip on fan-out wafer level packaging warpage using finite element analysis. It is assumed that Young's modulus of each chip follows the normal distribution. Simulation results show that the uncertainty of Young's modulus affects the maximum von Mises stress. As a result, it is necessary to control the uncertainty of Young's modulus of silicon chip since the maximum von Mises stress is a parameter related to the package reliability.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.53-58
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• 2003

The Wafer Level Packaging is one of the most important technologies in the semiconductor industry today. Its primary advantages are its small form factor and low cost potential for manufacturing including test procedure. The CASIO's WLP samples, application example and the structure are shown in Fig.1, 2&3. There are dielectric layer , under bump metal, re-distribution layer, copper post , encapsulation material and terminal solder .The key technologies are 'Electroplating thick copper process' and 'Unique wafer encapsulation process'. These are very effective in getting electrical and mechanical advantages of package. (Fig. 4). CASIO and CMK are developing a new System Packaging technology called the Embedded Wafer Level Package (EWLP) together. The active components (semiconductor chip) in the WLP structure are embedded into the Printed Wiring Board during their manufacturing process. This new technical approach has many advantages that can respond to requirements for future mobile products. The unique feature of this EWLP technology is that it doesn't contain any solder interconnection inside. In addition to improved electrical performance, EWLP can enable the improvement of module reliability. (Fig.5) The CASIO's WLP Technology will become the effective solution of 'KGD problem in System Packaging'. (Fig. 6) The EWLP sample shown in Fig.7 including three chips in the WLP form has almost same structure wi_th SoC's. Also, this module technology are suitable for RF and Analog system applications. (Fig. 8)

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.557-557
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• 2012

Silicatein-${\alpha}$, the enzyme extracted from silica spicules in glass sponges, has been studied extensively in the way of chemistry from 1999, in which the pioneering work by Morse, D. E. - the discovery of the enzymatic hydrolysis in Silicatein-${\alpha}$ - was published. Since its reaction conditions are physiologically favored, synthesis of various materials, such as gallium oxide, zirconium oxide, and silicon oxide, was achieved without any hazardous wastes. Although some groups synthesized oxide films and particles, they have not achieved yet controlled morphogenesis in the reaction conditions mentioned above. With the knowledge of catalytic triad involved in hydrolysis of silicone alkoxide and oligomerization of silicic acid, we designed the novel peptide amphiphiles to not only form self-assembled structure, but also display similar activities to silicatein-${\alpha}$. Designed templates were able to self-assemble into left-handed helices for the peptide amphiphiles with L-form amino acid, catalyzing polycondensation of silicic acids onto the surface of them. It led to the formation of silica helices with 30-50 nm diameters. These results were characterized by various techniques, including SEM, TEM, and STEM. Given the situation that nano-bio-technology, the bio-applicable technology in nanometer scale, has been attracting considerable attention; this result could be applied to the latest applications in biotechnology, such as biosensors, lab-on-a-chip, biocompatible nanodevices.

• Industrial Engineering and Management Systems
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• v.9 no.3
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• pp.227-241
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• 2010

A memory module industry's supply chain usually consists of multiple manufacturing sites and multiple distribution centers. In order to fulfill the variety of demands from downstream customers, production planners need not only to decide the order allocation among multiple manufacturing sites but also to consider memory module industrial characteristics and supply chain constraints, such as multiple material substitution relationships, capacity, and transportation lead time, fluctuation of component purchasing prices and available supply quantities of critical materials (e.g., DRAM, chip), based on human experience. In this research, a directed graph-based supply network planning (DGSNP) model is developed for memory module industry. In addition to multi-site order allocation, the DGSNP model explicitly considers production planning for each manufacturing site, and purchasing planning from each supplier. First, the research formulates the supply network's structure and constraints in a directed-graph form. Then, a proposed genetic algorithm (GA) solves the matrix form which is transformed from the directed-graph model. Finally, the final matrix, with a calculated maximum profit, can be transformed back to a directed-graph based supply network plan as a reference for planners. The results of the illustrative experiments show that the DGSNP model, compared to current memory module industry practices, determines a convincing supply network planning solution, as measured by total profit.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.1
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• pp.83-90
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• 1986

A micro pH-ISFET probe, which can be applied to the in vivo measurements of the hydrogen ion concentration in blood, has been developed, and a measuring system equiped with this probe also developed. The pH-ISFET has been fatricated by employing the techniques of integrated circuit fabrication. Two kinds of micro electrode formed around the sensing gate during the wafer process, and the other is a capillary type of Ag/AfCl/sat. KCI reduced in size. This capillary electrode has shown its good performance characteristics so far in the application with ISFET as well as a commercial one. In order to form a micro pH-ISFET probe, this pH-ISFET and well as a commercial one. In order to form a micro pH-ISFET probe, this pH-ISFET and the capillary electrode were built together into a needle tip having 1 mm inner diameter. The chip size of a twin pH-ISFET is 0.8 mmx1.4 mm, the material of the sensing gate membrane is Si3N4, and the sensitivity of the developed probe is about 52mV/pH.