• Title/Summary/Keyword: charge amplifier

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Development of capacitive Micromachined Ultrasonic Transducer (III) - Performance Test (미세가공 정전용량형 초음파 탐촉자 개발(III) - 탐촉자 성능평가)

  • Kim, Ki-Bok;Ahn, Bong-Young;Park, Hae-Won;Kim, Young-Joo;Lee, Seung-Seok
    • Journal of the Korean Society for Nondestructive Testing
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    • v.24 no.6
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    • pp.581-589
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    • 2004
  • In this study, the capacitive micromachined ultrasonic transducer(cMUT) was developed based on the previous research results. The cross sectional image of the developed cMUT was characterized. To measure the membrane displacement of the cMUT, the Michelson phase modulation fiber interferometer was constructed. The measured membrane displacement was in good agreement with the result of the finite element analysis. To estimate the ultrasonic wave generated by the cMUT, an ultrasonic system including a pulser, receiver and charge amplifier was used. The cMUT developed in this study shows a good performance and hence will be widely used in the non-contact ultrasonic applications.

A Capacitorless Low-Dropout Regulator With Enhanced Response Time (응답 시간을 향상 시킨 외부 커패시터가 없는 Low-Dropout 레귤레이터 회로)

  • Yeo, Jae-Jin;Roh, Jeong-Jin
    • Journal of IKEEE
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    • v.19 no.4
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    • pp.506-513
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    • 2015
  • In this paper, an output-capacitorless, low-dropout (LDO) regulator is designed, which consumes $4.5{\mu}A$ quiescent current. Proposed LDO regulator is realized using two amplifier for good load regulation and fast response time, which provide high gain, high bandwidth, and high slew rate. In addition, a one-shot current boosting circuit is added for current control to charge and discharge the parasitic capacitance at the pass transistor gate. As a result, response time is improved during load-current transition. The designed circuit is implemented through a $0.11-{\mu}m$ CMOS process. We experimentally verify output voltage fluctuation of 260mV and recovery time of $0.8{\mu}s$ at maximum load current 200mA.

Reliability verification of cutting force experiment by the 3D-FEM analysis from reverse engineering design of milling tool (밀링 공구의 역 공학 설계에서 3D 유한요소 해석을 통한 절삭력 실험의 신뢰성 검증)

  • Jung, Sung-Taek;Wi, Eun-Chan;Kim, Hyun-Jeong;Song, Ki-Hyeok;Baek, Seung-Yub
    • Design & Manufacturing
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    • v.13 no.2
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    • pp.54-59
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    • 2019
  • CNC(Computer Numerical Control) machine tools are being used in various industrial fields such as aircraft and automobiles. The machining conditions used in the mold industry are used, and the simulation and the experiment are compared. The tool used in the experiment was carried out to increase the reliability of the simulation of the cutting machining. The program used in the 3D-FEM (finite element method) was the AdvantEdge and predicted by down-milling. The tool model is used 3D-FEM simulation by using the cutting force, temperature prediction. In this study, we carried out the verification of cutting force by using a 3-axis tool dynamometer (Kistler 9257B) system when machining the plastic mold Steel machining of NAK-80. The cutting force experiment data using on the charge amplifier (5070A) is amplified, and the 3-axis cutting force data are saved as a TDMS file using the Lab-View based program using on NI-PXIe-1062Q. The machining condition 7 was the most similar to the simulation and the experimental results. The material properties of the NAK-80 material and the simulation trends reflected in the reverse design of the tool were derived similarly to the experimental results.

An Area-Efficient Time-Shared 10b DAC for AMOLED Column Driver IC Applications (AMOLED 컬럼 구동회로 응용을 위한 시분할 기법 기반의 면적 효율적인 10b DAC)

  • Kim, Won-Kang;An, Tai-Ji;Lee, Seung-Hoon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.5
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    • pp.87-97
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    • 2016
  • This work proposes a time-shared 10b DAC based on a two-step resistor string to minimize the effective area of a DAC channel for driving each AMOLED display column. The proposed DAC shows a lower effective DAC area per unit column driver and a faster conversion speed than the conventional DACs by employing a time-shared DEMUX and a ROM-based two-step decoder of 6b and 4b in the first and second resistor string. In the second-stage 4b floating resistor string, a simple current source rather than a unity-gain buffer decreases the loading effect and chip area of a DAC channel and eliminates offset mismatch between channels caused by buffer amplifiers. The proposed 1-to-24 DEMUX enables a single DAC channel to drive 24 columns sequentially with a single-phase clock and a 5b binary counter. A 0.9pF sampling capacitor and a small-sized source follower in the input stage of each column-driving buffer amplifier decrease the effect due to channel charge injection and improve the output settling accuracy of the buffer amplifier while using the top-plate sampling scheme in the proposed DAC. The proposed DAC in a $0.18{\mu}m$ CMOS shows a signal settling time of 62.5ns during code transitions from '$000_{16}$' to '$3FF_{16}$'. The prototype DAC occupies a unit channel area of $0.058mm^2$ and an effective unit channel area of $0.002mm^2$ while consuming 6.08mW with analog and digital power supplies of 3.3V and 1.8V, respectively.