• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.6
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• pp.1095-1102
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• 2010

This paper presents an equalizer reducing CCI(cell-to-cell interference) in MLC NAND flash memory. High growth of the flash memory market has been driven by two combined technological efforts that are an aggressive scaling technique which doubles the memory density every year and the introduction of MLC(multi level cell) technology. Therefore, the CCI is a critical factor which affects occurring data errors in cells. We introduced an equation of CCI model and designed an equalizer reducing CCI based on the proposed equation. In the model, we have been considered the floating gate capacitance coupling effect, the direct field effect, and programming methods of the MLC NAND flash memory. Also we design and verify the proposed equalizer using Matlab. As the simulation result, the error correction ratio of the equalizer shows about 20% under 20nm NAND process where the memory channel model has serious CCI.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.5
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• pp.50-57
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• 2007

A 5Gbps CMOS　adaptive feed-forward equalizer designed for backplane applications is described. The equalizer has adaptive feedback circuits to control the compensating gain of the equalizing filter, which uses a phase detector in clock recovery circuit to detect ISI (Inter-Symbol Interference) level. This makes the equalizer operate adaptively for a various channel length of backplane environments.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.5
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• pp.2347-2352
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• 2012

In this paper, a new alternating equalizer and its differential adjustment algorithm are proposed. The proposed alternating equalizer achieves equalization effectively using an algorithm performing symbol decisions based on soft/hard decision. In addition, it is possible to improve the initial blind convergence speed and steady-state error performance simultaneously by adjusting the equalizer differentially according to the relative reliability of the symbol decisions by soft/hard decision devices. The simulation results on 16/64-QAM constellations under multipath propagation channel and additive noise conditions confirmed to support usefulness of the proposed method.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.26-32
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• 2014

Single-Carrier Frequency division multiplexing (SC-FDM) has been selected for the uplink transmission technique in 3GPP-LTE since it has an advantage of low peak-to-average power ratio (PAPR) in user's perspective. The receiver typically uses a frequency domain equalizer, which, however, suffers from noise boost and/or residual ISI especially when the channel has deep nulls. In this paper, we propose using turbo equalizer to mitigate such a problem. We provide link level performance comparison and an insight into how many iteration is needed for reasonable performance and complexity.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.11 no.1
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• pp.29-34
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• 2011

In this paper, we propose and analyze the equalizer schemes, zero-forcing (ZF) and minimum mean square error (MMSE) in power line communication (PLC) system for automatic meter reading (AMR). For efficient implementation of AMR system with PLC, effects of impulsive noise and multipath channel should be mitigated. To overcome these effects, the above equalizer schemes are employed. System performance is evaluated in term of bit error rate. From simulation results, it is confirmed that the equalizer can significantly improve bit error rate (BER) performance in PLC system, and MMSE equalizer provides better performance than ZF scheme. The results of this paper can be applied to AMR system as well as various smart grid services using PLC.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.4
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• pp.318-324
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• 2013

For blind channel equalization, the reliability of signal estimate determines the convergence speed and steady-state performance of the equalizer. Therefore the nonlinear estimator and reference signal being used in signal estimate should be chosen appropriately. In this paper, to increase the reliability of the signal estimate, two errors were obtained by applying coarse signal points and dense signal points respectively to signal estimate, the relative reliabilities of two errors were calculated, then the equalizer was adapted deferentially utilizing the reliabilities. At this point, by applying two errors alternately, two modes of operation were smoothly combined. Through computer simulations the proposed method was confirmed to achieve fast transient state convergence and low steady-state error compared to traditional methods.

• Transactions of the Society of Information Storage Systems
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• v.1 no.2
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• pp.155-160
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• 2005

In this paper, the channel decoder promising reliable data retrieving in noisy holographic channel has been developed for holographic WORM(write once read many) system. It covers various DSP(digital signal processing) blocks, such as align mark detector, adaptive channel equalizer, modulation decoder and ECC(error correction code) decoder. The specific schemes of DSP are designed to reduce the effect of noises in holographic WORM(H-WORM) system, particularly in prototype of DAEWOO electronics(DEPROTO). For real time data retrieving, the channel decoder is redesigned for FPGA(field programmable gate array) based hardware, where DSP blocks calculate in parallel sense with memory buffers between blocks and controllers for driving peripherals of FPGA. As an input source of the experiments, MPEG2 TS(transport stream) data was used and recorded to DEPROTO system. During retrieving, the CCD(charge coupled device), capturing device of DEPROTO, detects retrieved images and transmits signals of them to the FPGA of hardware channel decoder. Finally, the output data stream of the channel decoder was transferred to the MPEG decoding board for monitoring video signals. The experimental results showed the error corrected BER(bit error rate) of less than $10^{-9}$, from the raw BER of DEPROTO, about $10^{-3}$. With the developed hardware channel decoder, the real-time video demonstration was possible during the experiments. The operating clock of the FPGA was 60 MHz, of which speed was capable of decoding up to 120 mega channel bits per sec.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.9A
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• pp.1346-1353
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• 1999

We propose the MADF(multiplication free adaptive digital filter) algorithm and implement the fractionally spaced equalizer based on it. To evaluate the performance of proposed MADF algorithm, fractionally spaced equalizer(FSE) is used. Especially, we present that this method have the advantages for the condition having the low-frequency and slow speed

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.3
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• pp.248-258
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• 1991

In this paper, ISI cancellation capabilites in the frequency selective fading channels of the equalizer emplouing individual tap LMS(ITLMS) algorithm and of th equalizer using the lattice structure have been investigated through the computer simulations in terms of bit error rate and convergence speed.

• Journal of electromagnetic engineering and science
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• v.4 no.2
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• pp.93-96
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• 2004

In this paper we introduce a new escalator(ESC) structure-based adaptation algorithm. The proposed algorithm is independent of eigenvalues spread ratio(ESR) of channel and has faster convergence speed than that of the conventional ESC algorithms. This algorithm combines the fast adaptation ability of least square methods and the orthogonalization property of the ESC structure. From the simulation results the proposed algorithm shows superior convergence speed and no slowing down of convergence speed when we increase the ESR of the channel.