• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.913-916
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• 2009

This paper describes a hardware design of hash processor which implements HAS-160 algorithm adopted as a Korean standard. To achieve a high-speed operation with small-area, the arithmetic operation is implemented using a hybrid structure of 5:3 and 3:2 carry-save adders and a carry-select adder. The HAS-160 processor synthesized with $0.35-{\mu}m$ CMOS cell library has 17,600 gates. It computes a 160-bit hash code from a message block of 512 bits in 82 clock cycles, and has 312 Mbps throughput at 50 MHz@3.3-V clock frequency.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.2
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• pp.53-64
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• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm, "Rijndael". An iterative looping architecture using a single round block is adopted to minimize the hardware required. To achieve high throughput rate, a sub-pipeline stage is added by dividing the round function into two blocks, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. The round block is implemented using 32-bit data path, so each sub-pipeline stage is executed for four clock cycles. The S-box, which is the dominant element of the round block in terms of required hardware resources, is designed using arithmetic circuit computing multiplicative inverse in GF($2^8$) rather than look-up table method, so that encryption and decryption can share the S-boxes. The round keys are generated by on-the-fly key scheduler. The crypto-processor designed in Verilog-HDL and synthesized using 0.25-$\mu\textrm{m}$ CMOS cell library consists of about 23,000 gates. Simulation results show that the critical path delay is about 8-ns and it can operate up to 120-MHz clock Sequency at 2.5-V supply. The designed core was verified using Xilinx FPGA board and test system.

• Journal of information and communication convergence engineering
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• v.4 no.4
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• pp.170-173
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• 2006

Recently, with increasing efficiency of DSC (photo-electrochemical using a nano-particle), The Performance of DSC solar generation system also needs improvement. The approach consists of a Fly-back DC-DC (transfer ratio 1:10) converter to boost the DSC cell voltage to 300VDC. The four switch (MOSFET) inverter is employed to produce 220V, 60Hz AC outputs. High performance, easy manufacturability, lower component count., safety and cost are addressed. Protection and diagnostic features form an important part of the design. Another highlight of the proposed design is the control strategy, which allows the inverter to adapt to the: requirements of the load as well as the power source. A unique aspect of the design is the use of the DSP TMS320LF2406 to control the inverter by current and voltage feed-back. Efficient and smooth control of the: power drawn from the DSC Cell is achieved by controlling the front end DC-DC converter in current mode.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.58 no.4
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• pp.639-643
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• 2009

A reformer, which produces hydrogen from natural gas, plays a major role for producing quality hydrogen to fuel-cell system. In this paper, fuel processor is designed to deliver hydrogen(75%) from the reformer to 200W fuel-cell system, and the electrical output power of the fuel-cells is examined by being injected different hydrogen concentrations to the system. We verified that the output power characteristics of the fuel-cells with 75% reformed hydrogen was lower about 7% than the case of pure hydrogen supplied. The type of reformer in this experiment takes SMR(Steam methane reforming) process, and the temperature variation characteristics of reforming process by reactions are examined in operation.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.01a
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• pp.751-754
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• 2009

This paper deals with the Cell-based distributed processing for generating free viewpoint images by merging multiple differently focused images. We previously proposed the method of generating free viewpoint images without any depth estimation. However, it is not so easy to realize real-time image reconstruction based on our previous method. In this paper, we discuss the method to reduce the processing time by dimension reduction for image filtering and Cell-based distributed processing. Especially, the method of high-speed image reconstruction by the Cell processor on SONY PLAYSTATION3(PS3) is described in detail. We show some experimental results by using real images and we discuss the possibility of real-time free viewpoint image reconstruction.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.226-229
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• 2000

In this paper, we describe implementation of 32-Bit RISC Core for portable communication/information equipment, such as cellular telephones and personal digital assistants, notebook, etc. The RISC core implements the ARM$\^$R/V4 instruction set on the basis of low power techniques in architecture level and logic level. It operates with 5-stage pipeline, and has harvard architecture to increase execution speed. The processor is modeled and simulated in RTL level using VHDL. Behavioral Cache and MMU are added to the VHDL model for instruction level verification of the processor. The core is implemented using Mentor P'||'&'||'R tools with IDEC C-631 Cell library of 0.6$\mu\textrm{m}$ CMOS 1-poly 3-metal CMOS technology.

• Journal of information and communication convergence engineering
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• v.6 no.4
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• pp.376-382
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• 2008

Developing highly cost-efficient and reliable embedded systems demands hardware/software co-design and co-simulation due to fast TTM and verification issues. So, it is essential that Platform-Based SoC design methodology be used for enhanced reusability. This paper addresses a reusable SoC platform based on OpenCores soft processor with reconfigurable architectures for hardware/software codesign methodology. The platform includes a OpenRISC microprocessor, some basic peripherals and WISHBONE bus and it uses the set of development environment including compiler, assembler, and debugger. The platform is very flexible due to easy configuration through a system configuration file and is reliable because all designed SoC and IPs are verified in the various test environments. Also the platform is prototyped using the Xilinx Spartan3 FPGA development board and is implemented to a single chip using the Magnachip cell library based on $0.18{\mu}m$ 1-poly 6-metal technology.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.1
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• pp.46-54
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• 2002

Plasma Display Panel (PDP) is required to be both the determination of white point of each gray level and the inverse gamma correction since no-balanced RGB cell and linear property of PDP, respectively. However, these two methods cause degradation of grey level representation and undesirable false contour in the dark areas on PDP. In this paper, we implemented real time image processor of the proposed error diffusion algorithm and unsharp masking operation to protect the blurring image caused by the error diffusion. Experimental results showed drastic improvements of gray level representation and reduction of undesirable false contour.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.835-838
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• 1998

본 연구에서는 칼라 CCD 센서를 제어하여, shading과 .gamma. correction 된 데이터를 읽어 들여, 이를 이진레벨 데이터로 바꾼후, 원래의 다치레벨 또는 이진레벨 데이터를 SCSI나 DMA I/F를 통해 전달하는 ASIC을 설계하였다. 본 ASIC에서는 이진화를 위하여 문자 모드에서는 simple threshold와 LAT(local adaptive threshold) 알고리즘을, 그림모드에서는 stucki error diffusion 알고리즘을 적용하였다. 그리고, 구성은 CCD센서 제어블락, 스텝 모타 제어제어블락, 이미지 축소블락, 데이터 이진화 블락, 그리고 DATA I/F 블락 등으로 이루어져 있다. 또한 사용된 technology는 삼성 0.5um CMOS standard cell이며, 크기는 45K gates(내부 메모리 제외)이고, 160QFP package로 구현되었다. ㅎㅁㅅㄷㄴ (soqn apa

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.357-360
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• 2000

In this paper, we designed 32-Hit MAC architecture of a RISC Processor for portable terminals such as cellular telephones, personal digital assistants, notebooks, etc. In order to have minimum area with best performance, the MAC performs 32 by 8 multiplication per cycle, with early termination circuit that enables multiply cycles depend on the value of multiplier. It uses the sign bit of a partial product and two extra bits for sign extension, The MAC is modeled and simulated in RTL using VHDL. The MAC is synthesized using IDEC C-631 Cell library based on 0.6$\mu\textrm{m}$ CMOS 1-Poly 3-metal CMOS technology.